Controlled Buckling Structures in Semiconductor Interconnects and Nanomembranes for Stretchable Electronics

ABSTRACT

In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/851,182 filed Sep. 6, 2007, which claims the benefit of U.S.Provisional Patent Applications 60/944,626 filed Jun. 18, 2007 and60/824,683 filed Sep. 6, 2006 and is a continuation-in-part of U.S.patent application Ser. Nos. 11/145,574 filed Jun. 2, 2005, and11/145,542 filed Jun. 2, 2005, each of which claim benefit of U.S.Provisional Patent Application Nos. 60/577,077, 60/601,061, 60/650,305,60/663,391 and 60/677,617 filed on Jun. 4, 2004, Aug. 11, 2004, Feb. 4,2005, Mar. 18, 2005, and May 4, 2005, respectively, and is also acontinuation-in-part of Ser. No. 11/423,287 filed Jun. 9, 2006 whichclaims benefit of 60/790,104 filed Apr. 7, 2006, and is acontinuation-in-part of U.S. patent application Ser. Nos. 11/145,574filed Jun. 2, 2005, and 11/145,542 filed Jun. 2, 2005, all of which arehereby incorporated by reference in their entirety to the extent notinconsistent with the disclosure herein

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with government support under DEFG02-91-ER45439awarded by U.S. Department of Energy. The government has certain rightsin the invention.

BACKGROUND OF THE INVENTION

Since the first demonstration of a printed, all polymer transistor in1994, a great deal of interest has been directed at a potential newclass of electronic systems comprising flexible integrated electronicdevices on plastic substrates. [Garnier, F., Hajlaoui, R., Yassar, A.and Srivastava, P., Science, Vol. 265, pgs 1684-1686] Recently,substantial research has been directed toward developing new solutionprocessable materials for conductors, dielectrics and semiconductorselements for flexible plastic electronic devices. Progress in the fieldof flexible electronics, however, is not only driven by the developmentof new solution processable materials but also by new device componentgeometries, efficient device and device component processing methods andhigh resolution patterning techniques applicable to flexible electronicsystems. It is expected that such materials, device configurations andfabrication methods will play an essential role in the rapidly emergingnew class of flexible integrated electronic devices, systems andcircuits.

Interest in the field of flexible electronics arises out of severalimportant advantages provided by this technology. For example, theinherent flexibility of these substrate materials allows them to beintegrated into many shapes providing for a large number of usefuldevice configurations not possible with brittle conventional siliconbased electronic devices. In addition, the combination of solutionprocessable component materials and flexible substrates enablesfabrication by continuous, high speed, printing techniques capable ofgenerating electronic devices over large substrate areas at low cost.

The design and fabrication of flexible electronic devices exhibitinggood electronic performance, however, present a number of significantchallenges. First, the well developed methods of making conventionalsilicon based electronic devices are incompatible with most flexiblematerials. For example, traditional high quality inorganic semiconductorcomponents, such as single crystalline silicon or germaniumsemiconductors, are typically processed by growing thin films attemperatures (>1000 degrees Celsius) that significantly exceed themelting or decomposition temperatures of most plastic substrates. Inaddition, most inorganic semiconductors are not intrinsically soluble inconvenient solvents that would allow for solution based processing anddelivery. Second, although many amorphous silicon, organic or hybridorganic-inorganic semiconductors are compatible with incorporation intoflexible substrates and can be processed at relatively low temperatures,these materials do not have electronic properties capable of providingintegrated electronic devices capable of good electronic performance.For example, thin film transistors having semiconductor elements made ofthese materials exhibit field effect mobilities approximately threeorders of magnitude less than complementary single crystalline siliconbased devices. As a result of these limitations, flexible electronicdevices are presently limited to specific applications not requiringhigh performance, such as use in switching elements for active matrixflat panel displays with non-emissive pixels and in light emittingdiodes.

Flexible electronic circuitry is an active area of research in a numberof fields including flexible displays, electro-active surfaces ofarbitrary shapes such as electronic textiles and electronic skin. Thesecircuits often are unable to sufficiently conform to their surroundingsbecause of an inability of the conducting components to stretch inresponse to conformation changes. Accordingly, those flexible circuitsare prone to damage, electronic degradation and can be unreliable underrigorous and/or repeated conformation change. Flexible circuits requirestretchable and bendable interconnects that remain intact while cyclingthrough stretching and relaxation.

Conductors that are capable of both bending and elasticity are generallymade by embedding metal particles in an elastomer such as silicone.Those conductive rubbers are both mechanically elastic and electricallyconductive. The drawbacks of a conductive rubber include high electricalresistivity and significant resistance changes under stretching, therebyresulting in overall poor interconnect performance and reliability.

Gray et al. discuss constructing elastomeric electronics usingmicrofabricated tortuous wires encased in a silicone elastomer capableof linear strains up to 54% while maintaining conductivity. In thatstudy, the wires are formed as a helical spring-shape. In contrast tostraight-line wires that fractured at low strains (e.g., 2.4%), tortuouswires remained conductive at significantly higher strains (e.g., 27.2%).Such a wire geometry relies on the ability of wires to elongate bybending rather than stretching. That system suffers limitations in theability to controllably and precisely pattern in different shapes and inadditional planes, thereby limiting the ability to tailor systems todifferent strain and bending regimes.

Studies suggest that elastically stretchable metal interconnectsexperience an increase in resistance with mechanical strain. (Mandlik etal. 2006). Mandlik et al. attempt to minimize this resistance change bydepositing metal film on pyramidal nanopatterned surfaces. That study,however, relies on the relief feature to generate microcracks thatimpart stretchability to thin metal lines. The microcracks facilitatemetal elastic deformation by out of plane twisting and deformation.Those metal cracks, however, are not compatible with thick metal films,and instead is compatible with a rather narrow range of thin metal films(e.g., on the order of less than 30 nm) that are deposited on top ofpatterned elastomer.

One manner of imparting stretchability to metal interconnects is byprestraining (e.g., 15%-25%) the substrate during conductor (e.g.,metal) application, followed by spontaneous relief of the prestain,thereby inducing a waviness to the metal conductor interconnects. (see,e.g., Lacour et al. (2003); (2005); (2004), Jones et al. (2004); Huck etal. (2000); Bowden et al. (1998)). Lacour et al. (2003) report byinitially compressing gold stripes to generate spontaneously wrinkledgold stripes, electrical continuity is maintained under strains of up to22% (compared to fracture strains of gold films on elastic substrates ofa few percent). That study, however, used comparatively thin layers ofmetal films (e.g., about 105 nm) and is relatively limited in that thesystem could potentially make electrical conductors that could bestretched by about 10%.

From the forgoing, it is apparent there is a need for interconnects anddevice components having improved stretchability, electrical propertiesand related processes for rapid and reliable manufacture of stretchableinterconnects in a variety of different configurations. Progress in thefield of flexible electronics is expected to play a critical role in anumber of important emerging and established technologies. The successof these applications of flexible electronics technology dependsstrongly, however, on the continued development of new materials, deviceconfigurations and commercially feasible fabrication pathways for makingintegrated electronic circuits and devices exhibiting good electronic,mechanical and optical properties in flexed, deformed and bentconformations. Particularly, high performance, mechanically extensiblematerials and device configurations are needed exhibiting usefulelectronic and mechanical properties in stretched or contractedconformations.

SUMMARY OF THE INVENTION

The present invention provides stretchable devices and device componentssuch as semiconductors and stretchable electronic devices, and circuits.Stretchable, bendable and conformable electronic devices and devicecomponents are required for making electronics suitable for printing ona variety of curved surfaces. Shape-conforming devices have a variety ofapplications ranging from flexible displays and electronic fabrics toconformable biological and physical sensors. Accordingly, an embodimentof the invention are flexible and bendable electronic devices, devicecomponents, and related methods for making flexible and bendabledevices. Such flexibility and bendability is accomplished by providingan interconnect or semiconductor membrane having a wavy or buckledgeometry. Such geometry provides a means for ensuring the system isstretchable and bendable without adversely impacting performance, evenunder vigorous and repeated stretching and/or bending cycles.Furthermore, the methods provide a capability of precise and accurategeometric construction, so that physical characteristics (e.g.,stretchability, bendability) of the device and/or device component maybe tailored to the operating conditions of the system. Another aspect ofthe invention are stretchable components having a physical property thatis at least partially coupled to strain, so that the parameter iscapable is capable of being tuned by application of varying amount ofstrain to the component.

An array of device components may be connected to one another by buckledcomponents or interconnects, to facilitate independent movement ofdevice components relative to one another. Local regions within thearray, however, may have a different bending or stretching requirementthan other regions. The devices and methods presented herein facilitateconstruction of a flexible system that can have localized variation inbuckled component or interconnect geometry including component orinterconnect dimension, periodicity, amplitude, orientation, and totalnumber of components or interconnects in an area, for example.Generating multiple components or interconnects having controllableorientation facilitates tailoring components or interconnects to thedevice's operating conditions.

In an embodiment, the invention is a stretchable component of a device,where the component comprises a first end, a second end, and a centralregion disposed between the first and second ends. The component issupported by a substrate, with the first end and second ends of thecomponent bonded to the substrate, and at least a portion of the centralregion of the component having a bent configuration. In an aspect, thecentral region of the component is not in physical contact with thesubstrate. In another aspect, the central region of the component isunder strain. In an aspect, the strain in the central region is lessthan 10%, between 0.1% and 5%, 0.1% and 2%, or any sub-ranges thereof.

In an embodiment, the stretchable component central portion is curved orarc-shaped. In an aspect, the curve has an amplitude, such as anamplitude that is between about 100 nm and 1 mm. In an aspect, thenumber of distinct component or interconnect bond regions may numbermore than two, such as three, four, or five, for example. In thisaspect, the central portion that is between the first and secondcomponent ends is actually subdivided into a number of bentconfiguration regions, so that a plurality of distinct curved portionregions not in physical contact with the substrate are formed. In such aconfiguration, the amplitude and/or periodicity may be constant or mayvary over the entire longitudinal length of the component orinterconnect. The component itself may be of any shape, such as amembrane, wire, or a ribbon. In an aspect where the component is aribbon, the ribbon may have a thickness that is between about 300 nm and1 mm.

To facilitate placement of additional device components, the devicecomponent to which a component end is electrically connected may be acontact pad. In an aspect, an additional device component is inelectrical contact with the contact pad.

The stretchable component optionally comprises one or more materialsthat is a metal, a semiconductor, an insulator, a piezoelectric, aferroelectric, a magnetostrictive material, an electrostrictivematerial, a superconductor, a ferromagnetic material, or athermoelectric material.

In another aspect, the stretchable component comprises a component of adevice selected from the group consisting of an electronic device, anoptical device, an opto-electronic device, mechanical device and athermal device.

As noted, the substrate that supports the component may be of anydesired material depending on the device in which the component isincorporated. In an embodiment, the substrate comprises an elastomericmaterial, such as PDMS. The substrate may be reversibly deformable(e.g., PDMS) or non-reversibly deformable (e.g., a plastic). In anembodiment, the substrate itself is a layer or coating.

In an embodiment, the devices may be further described based on theirphysical characteristics. For example, provided herein are componentsand/or interconnects capable of undergoing a strain of up to 25% whilemaintaining electrical conductivity and electrical contact with thedevice component. “Maintaining” in this case refers to less than a 20%,10% or 5% drop in electrical conductivity during strain accommodation.

In another embodiment, the invention provides a stretchable component orinterconnect for establishing electrical contact with device components.The component or interconnect has a first end, a second end and acentral portion disposed between the first and second ends. The ends arebonded to a substrate, such as a flexible (e.g., stretchable) substrate,an elastomeric substrate, a rigid substrate, a substrate that is notelastomeric, or a substrate to which it is desired to print electronicdevices, device components, or arrays thereof. Each end of the componentor interconnect may be attached to a different device component that isitself supported by the substrate. The central portion of the componentor interconnect is in a bent configuration and not in physical contact(e.g., not bonded) with the substrate. In an aspect, this bentconfiguration is a result of the central portion being under strain. Inthis aspect, the bent configuration is generally curved so that if aforce is applied to one or more device components (or underlyingsubstrate) in a manner that separates the device components, thecomponent or interconnect curved portion may at least partiallystraighten to accommodate relative motion between the device components,while maintaining electrical contact between the device components. Thecomponents or interconnects optionally electrically connect adjacentislands or contact pads in any one of a number of geometries such asbridge, floral and/or by multiple components or interconnects. In anaspect, a device component is in electrical contact with the contactpad.

Any of the stretchable components disclosed herein optionally furthercomprise a tunable device component of an electronic device. The tunablecomponent has at least one electronic property that changes selectivelywith the strain of the central region provided by said bentconfiguration. For example, the electronic property is optionally one ormore of electron mobility, resonance frequency, conductance, andresistance. In an aspect, the tunable device component comprises thesemiconductor channel of a transistor.

In an embodiment, the component has a strain coefficient opticalcoupling, where the tunable component has at least one optical propertythat changes selectively with the level of strain of the central regionprovided by the bent configuration. Example of strain coefficientoptical coupling includes, but is not limited to, the refractive indexof the tunable device component or the angle of incidence of a incidentbeam of electromagnetic radiation relative to a surface of the centralregion of the stretchable component. In another embodiment, the tunabledevice component comprises a waveguide, an optical modulator, an opticalswitch, or an optical filter.

In another embodiment, the stretchable component is a tunable devicecomponent of a device having thermal conductivity that changesselectively with the level of strain in the central region provided bythe bent configuration.

In another embodiment, the stretchable component is a thermal isolationcomponent of a device, wherein the central region is not in physicalcontact with said substrate. In an aspect of this embodiment, thecentral region is not in thermal contact with the substrate, and thecentral region supports one or more device components, thereby providingthermal isolation of the one or more device components supported by thecentral region from the substrate. A useful application for this aspectis for a device that is a long wavelength imaging system.

In another embodiment, the stretchable component is an actuator of amechanical device, wherein the central region is curved and has anamplitude that is capable of modulation by compressing or elongatingsaid stretchable component or by applying an electric potential to saidcentral region. A useful application in this embodiment is a mechanicaldevice that is selected from the group consisting of amicroelectromechanical device, a nanoelectromechanical device, and amicrofluidic device.

In an embodiment, multi-axial stretching and bending is provided byincorporating any of the stretchable components disclosed herein into adevice array having a plurality of components and more than two devicecomponents. In this embodiment, each component provides electricalcontact between a pair of device components. Depending on the desiredstretching, bending and/or compression operating conditions, the devicearray may have a geometric configuration that is in a grid, floral,bridge or any combination thereof (e.g., one region that is in a grid,another region that is bridge). In addition, further stretching andbendability control is provided by the ability to connect adjacentdevice components to more than one components (e.g., multipleinterconnects), such as two, three, or four components. For example, adevice component that is square or rectangular, may be adjacent to fourother device components. If each adjacent pair is connected by twointerconnects, the device component will have eight interconnectsextending therefrom.

In an embodiment, a device array has sets of components that areoriented in at least two different directions. For example, in a gridconfiguration the components may have two orientations that areperpendicular or orthogonal to one another to provide capacity forstretching in two directions. In another embodiment, the device arraymay comprise components that are all aligned with respect to each other.That embodiment may be useful where stretching or bending is confined toa single direction (e.g., bending an electronic device fabric to acylindrical surface). Additional bending and/or stretching capacity isprovided by orienting the components in three or more directions, threedirections or four directions, for example. In an embodiment, additionalcontrol and stability is provided by having the components of the devicearray placed in any number of different layers, such as two layersadjacent to one another.

In an embodiment, a device array is capable of undergoing a strain of upto about 150% without fracturing. Strain to fracture is maximized bytailoring the interconnect geometry, orientation, amplitude,periodicity, number to the operating conditions (e.g., uniaxial versusmultiaxial stretching and/or bending).

The substrate to which the interconnect or device array is supported mayhave at least a portion that is curved, such as in a concave, convex,hemispherical shape, or combination thereof. In an embodiment, thedevice in which the components is incorporated is one or more of astretchable: photodetector, display, light emitter, photovoltaic, sheetscanner, LED display, semiconductor laser, optical system, large-areaelectronics, transistor, or an integrated circuit.

In another aspect, the present invention relates to various methods fortuning a property of a stretchable component of a device. For example, atuning method may comprise providing a device having a stretchablecomponent, as disclosed herein, such as a component having a first end;a second end; and a central region disposed between the first and secondends, and that is supported by a substrate. In particular, the first endand second end of the component are bonded to the substrate, and atleast a portion of the central region of the component has a bentconfiguration and is under a level of strain. The level of strain ismodulated in the stretchable component by compressing, elongating and/orbending the stretchable component, thereby tuning the property of thestretchable component of the device.

In an aspect, the property is one or more of an optical property, anelectrical property, and a mechanical property, such as an optically,mechanically, or electrically-coupled strain parameter, where themagnitude of the respective property is at least partiallystrain-dependent . In another aspect, the property is selected from thegroup consisting of resonance frequency, electron mobility, resistance,conductance, refractive index, thermal conductivity, and the angle ofincidence of an incident beam of electromagnetic radiation relative to asurface of the central region of said stretchable component.

In an embodiment, provided is a method of making a stretchable componentof a device. In this embodiment, an elastomeric substrate having areceiving surface is provided having a first level of strain, where thestrain is optionally zero, compressive, or elongating. One or moredevice components are bonded to the receiving surface having the firstlevel of strain. A force is applied to the elastomeric substrate so asgenerate a change in the level of strain from the first to a seconddifferent level of strain. The magnitude of this change, or how thechange is accomplished does not particularly matter so long as thechange in the level of strain in the substrate from the first level tothe second level causes the component to bend, thereby generating theone or more stretchable components each having a first end and secondend that are bonded to the substrate and a central region provided in abent configuration.

Bonding of the device components to the substrate is by any suitablemeans. In an embodiment, the bonding step comprises generating a patternof bonded and non-bonded regions of the stretchable component, whereinthe bonded regions of the stretchable component are bonded to theelastomeric substrate and wherein the non-bonded regions of saidstretchable component are not bonded to the elastomeric substrate.

In another aspect, non-bonded regions correspond to central regions ofthe stretchable components, wherein the step of applying the force tothe elastomeric substrate causes the central regions to bend such thatat least a portion of the central region of each stretchable componentis not in physical contact with the substrate. In an aspect, the step ofapplying the force to the elastomeric substrate causes central regionsto bend such that at least a portion of the central region of eachstretchable component is not in physical contact with the substrate.

In an embodiment, any of the methods for making a stretchable componentfurther comprises generating a pattern of bonding sites on thestretchable component, the receiving surface of the elastomericsubstrate or on both the stretchable component and the receiving surfaceof the elastomeric substrate.

In another embodiment, any of the methods or devices have an elastomericsubstrate with a plurality of compliant regions and a plurality of rigidregions. Such a substrate provides flexural rigidity of the compliantregions that is less than that of the rigid regions, and optionally havethe first and second ends of each of the stretchable components bondedto at least one of the rigid regions and a central region of each of thestretchable components bonded to at least one of the compliant regions.Use of this substrate type provides the capacity of achievingcontrollable buckling of the component based on the pattern ofcompliancy of the underlying substrate.

In an embodiment, the force applied to the elastomeric substrate isachieved mechanically. In an aspect of this embodiment, the first levelof strain, the second level of strain or both are generated byelongating or compressing the elastomeric substrate, curing theelastomeric substrate, or by thermal means, such as by raising orlowering the temperature of said elastomeric substrate, or by thermalexpansion or thermally induced contraction of the elastomeric substrate.

In another embodiment, the step of bonding the one or more devicecomponents to said receiving surface of said elastomeric substrate iscarried out before the step of applying a force to the elastomericsubstrate that generates a change in the level of strain of thesubstrate from the first level to a second level of strain differentthan said first level. Alternatively, the step of bonding is carried outafter the step of applying a force to the elastomeric substrate thatgenerates a change in the level of strain of the substrate from thefirst level to a second level of strain different than the first level.

In an embodiment, any of the first level of strain or second level ofstrain is equal to 0. In an aspect, any of the device componentscomprises an interconnect or an electrode.

In another embodiment, the invention relates to various methods formaking a buckled component or interconnect capable of establishingelectrical contact with device components. In an aspect, a pattern ofbond sites is applied to an elastomeric substrate surface, thecomponents or interconnects, or to both. A force is exerted to strainthe substrate and the components or interconnects contacted with thesubstrate. The pattern of bond sites provides bonding between specificcomponents or interconnect locations and the substrate. Upon relaxationof the substrate (by removal of the force), buckled components orinterconnects are generated. Varying one or more of the magnitude ofprestrain, bond site patterning, geometry and spacing generatescomponents or interconnects with different buckled or wavy geometry. Forexample, staggering the location of bond sites so that adjacentcomponents or interconnects are bonded to the substrate at differentlocations, provides an “out-of-phase” interconnect geometry. Bond sitepatterning is by any means known in the art, such as by application of acurable photopolymer to the elastomeric substrate surface. Components orinterconnects are optionally protected by encapsulating at least aportion of the component or interconnect in an encapsulating material,such as an elastomeric material. The buckled components or interconnectsmay have any pattern suited for the application. In an embodiment, thepattern is a grid configuration, floral configuration, bridgeconfiguration, or any combination thereof.

The methods and devices may have components of any dimensions, such as athickness ranging from tens of nanometers to about a millimeter, or athickness greater than about 300 nm. In an aspect, the buckled componenthas an amplitude corresponding to a maximum vertical displacement of theinterconnect from the substrate, and the amplitude is selected from arange that is between 100 nm and 1 mm. For a component ribbon having alength and a width, the width, the amplitude, or the width and amplitudeoptionally varies along the length of the interconnect. One factor thataffects amplitude, is the strain applied to the elastomeric substrateprior to component bonding or after the component bonding. In general,the higher the strain, the larger the amplitude. In an embodiment, theapplied force generates a strain in the elastomeric substrate, whereinthe strain selected from a range that is between 20% and 100%.

In an embodiment, the component is an interconnect electricallyconnected to a device component. Any of the systems and processespresented herein optionally provide for a substrate that is capable ofstretching up to about 100%, compressing up to about 50%, or bendingwith a radius of curvature as low as 5 mm, without component fracture.The component is made from any suitable material, such as a metal, asemiconductor, including GaAs or Si, an insulator, a piezoelectric, aferroelectric, a magnetostrictive material, an electrostrictivematerial, a superconductor, a ferromagnetic material, and athermoelectric material. In an embodiment, the methods provide fortransfer printing of the buckled components from an elastomericsubstrate, such as a stamp, to a device substrate such as, for example,a curved device substrate.

Instead of generating pop-up or buckled components via force or strainapplication to an elastomeric substrate, a stretchable and bendableinterconnect may be made by application of a component material to areceiving surface, such as a receiving surface having relief features,such as a wavy surface.

In an embodiment, to make a stretchable and bendable component asubstrate with wavy features on a surface is smoothed, such asspin-coating a polymer to partially fill the recess features. Thepartial filling generates a smoothly-wavy substrate. Components,including but not limited to metal features, are then deposited andpatterned as desired onto the smoothly-wavy substrate. The components onthe receiving surface substrate are available for subsequent casting ofa polymeric stamp against the substrate at least partially coated withthe component. The component is transferred to the polymeric substrateby removing the polymeric stamp from the substrate to make a stretchableand bendable component. In an embodiment, the interface between thecomponent and substrate is Au/Su-8 epoxy photoresist. The component maybe a layered metal, for example, Au/Al. The substrate may be similarlylayered, for example a glass layer supporting the Su-8 layer, with theactual interface between the metal and the substrate being Au/Su-8.

An alternative method of making a pop-up component, such as a pop-upinterconnect, on a stamp surface relies on flattening a curved substratesurface, contacting components to the flattened surface, and allowingthe substrate surface to relax back to its curved geometry. In anembodiment, the method further provides spatial patterning of bond sitesprior to contact, as disclosed herein. In this embodiment, the method isparticularly suited for transferring interconnects and device componentsto a second corresponding curved substrate surface. In an aspect,bonding means, such as adhesive or adhesive precursor generates bondingbetween the second curved substrate and interconnect system on the firstcurved substrate, sufficient to permit transfer of interconnect systemto the second substrate, even after the elastomeric stamp is removed.

Any of the methods and devices of the present invention, in an aspect,has a stamp or elastomeric substrate that is PDMS having a linear andelastic response for strains that are up to about 40%. The interconnectsof the present invention are optionally part of a stretchable electrode,stretchable passive matrix LED display, or a photodetector array. In anembodiment, the invention is a stretchable electronic device with anyone or more interconnects made by the methods of the present invention,where the electronic device is a stretchable or bendable: electrode,passive matrix LED, solar cell, optical collector arrays, biosensor,chemical sensor, photodiode array, or semiconductor array. In an aspect,the device component that is electrically connected to the buckledinterconnect is a thin film, sensor, circuit element, control element,microprocessor, transducers, or combinations thereof. In an aspect,interconnects are accessed by electrically connecting one end of theinterconnect to a device component.

In an embodiment, the invention relates to methods and structures havinga wavy nanomembrane, such as a wavy semiconductor nanomembrane. Such awavy nanomembrane facilitates incorporation of flexibility in a devicecomponent itself (in contrast to flexibility of the interconnects thatconnect device components). In an aspect, the invention is a method ofmaking a biaxially stretchable semiconductor membrane transferring asemiconductor nanomembrane material from a first substrate to a seconddeformed substrate, wherein after transfer the deformed substrate ispermitted to relax back to its resting configuration. In an aspect, thethickness of the semiconductor material is between about 40 nm and 600nm. Release of a two-dimensional deforming force generates ananomembrane having a two-dimensional wavy structure. In an aspect, thedeforming force is generated by changing the temperature of the flexiblesubstrate.

In an embodiment, a method is provided for making a stretchable andbendable device comprising providing a substrate having a receivingsurface with relief features; smoothing the relief features byspin-coating a polymer to at least partially conformally coat thereceiving surface; casting a polymeric stamp against the spin-coatedsubstrate; removing the polymeric stamp from the substrate to expose apolymeric stamp having relief features; and depositing a devicecomponent onto the polymeric stamp surface having relief features;thereby making a stretchable and bendable component for use in astretchable and bendable device. In an aspect, the relief features arewavy.

In an embodiment, the component comprises a metal, and the metal isdeposited by electrodeposition or by: providing a shadowmask; contactingthe shadowmask with the wavy surface; and evaporating metal through theshadowmask to generate a corresponding pattern of metal on the wavysurface. The substrate having wavy features is optionally made byanisotropic etching of Si (1 0 0) or by embossing Su-8. The wavy surfaceoptionally has a wavelength having a range selected from between 50 nm-1mm; an amplitude having a range selected from between 100 nm-1 mm; andis capable of stretching up to 100% without fracture. Optionally thecomponent is transferred to a device substrate. In an aspect, the devicecomponent comprises an interconnect, and the method further comprisesproviding an additional device component and establishing an electricalcontact between one end of the interconnect and the additional devicecomponent.

In another aspect, the present invention provides methods of making adevice via materials level heterogeneous integration and/or device levelheterogeneous integration techniques. A method of the present inventionfor making a device comprises the steps of: (i) providing a substratepre-patterned with one or more device components supported by areceiving surface of the substrate; and (ii) assembling a plurality ofprintable semiconductor elements on the substrate by contact printingthe printable semiconductor elements onto the receiving surface of thesubstrate or one or more structures provided thereon, wherein at least aportion of the printable semiconductor elements are positioned such thatthey are spatially aligned, in electrical contact or both with one ormore of the device components supported by the substrate. In anembodiment, the printable semiconductor elements each comprise a unitaryinorganic semiconductor structure having a length selected from therange of about 100 nanometers to about 1000 microns, a width selectedfrom the range of about 100 nanometers to about 1000 microns, and athickness selected from the range of about 10 nanometers to about 1000microns.

In another aspect, the present invention provides methods of makingmultilevel device structures via materials level heterogeneousintegration and/or device level heterogeneous integration techniques. Amethod of the present invention for making a device comprises the stepsof: (i) providing a substrate pre-patterned with one or more devicecomponents supported by a receiving surface of the substrate; (ii)assembling a first set of printable semiconductor elements on thesubstrate by contact printing the printable semiconductor elements ontothe receiving surface of the substrate or one or more structuresprovided thereon, thereby generating a first device layer; (iii)providing an interlayer on the first set of printable semiconductorelements, the interlayer having a receiving surface; and (iv) assemblinga second set of printable semiconductor elements on the interlayer bycontact printing the printable semiconductor elements onto the receivingsurface of the interlayer or one or more structures provided thereon,thereby generating a second device layer. In an embodiment, at least aportion of the printable semiconductor elements in the first devicelayer are spatially aligned, in electrical contact or both with at leasta portion of the printable semiconductor elements in the second devicelayer. A specific method of this aspect of the present invention furthercomprises the step of establishing electrical contact between at least aportion of the printable semiconductor elements in the first devicelayer and at least a portion of the printable semiconductor elements inthe second device layer.

Useful contact printing methods for assembling, organizing and/orintegrating printable semiconductor elements in the present methodsinclude dry transfer contact printing, microcontact or nanocontactprinting, microtransfer or nanotransfer printing and self assemblyassisted printing. Use of contact printing is beneficial in the presentinvention because it allows assembly and integration of a plurality ofprintable semiconductor in selected orientations and positions relativeto each other. Contact printing in the present invention also enableseffective transfer, assembly and integration of diverse classes ofmaterials and structures, including semiconductors (e.g., inorganicsemiconductors, single crystalline semiconductors, organicsemiconductors, carbon nanomaterials etc.), dielectrics, and conductors.Contact printing methods of the present invention optionally providehigh precision registered transfer and assembly of printablesemiconductor elements in preselected positions and spatial orientationsrelative to one or more device components prepatterned on a devicesubstrate. Contact printing is also compatible with a wide range ofsubstrate types, including conventional rigid or semi-rigid substratessuch as glasses, ceramics and metals, and substrates having physical andmechanical properties attractive for specific applications, such asflexible substrates, bendable substrates, shapeable substrates,conformable substrates and/or stretchable substrates. Contact printingassembly of printable semiconductor structures is compatible, forexample, with low temperature processing (e.g., less than or equal to298K). This attribute allows the present optical systems to beimplemented using a range of substrate materials including those thatdecompose or degrade at high temperatures, such as polymer and plasticsubstrates. Contact printing transfer, assembly and integration ofdevice elements is also beneficial because it can be implemented via lowcost and high-throughput printing techniques and systems, such asroll-to-roll printing and flexographic printing methods and systems.

In specific embodiments of the present methods of making devices atleast a portion of the printable semiconductor elements compriseheterogeneous semiconductor elements. A range of heterogeneoussemiconductor elements are useful in the present invention. In anembodiment, or example, the heterogeneous semiconductor elementscomprise an inorganic semiconductor structure in combination with one ormore structures comprising a material selected from the group consistingof: an inorganic semiconductor having a different composition than theinorganic semiconductor structure, an inorganic semiconductor having adifferent doping than the inorganic semiconductor structure, a carbonnanomaterial or film thereof, an organic semiconductor, a dielectricmaterial, and a conductor. In an embodiment, for example, theheterogeneous semiconductor elements comprise a combination of twodifferent semiconductor materials selected from the group consisting ofsingle crystal silicon, Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs,GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS, CdSe,ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs,AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, SiGe and GaInAsP. In anembodiment, for example, the heterogeneous semiconductor elementscomprise the inorganic semiconductor structure in combination with adielectric material, a conductor or both a dielectric material and aconductor.

Useful heterogeneous semiconductor elements also include printabledevice components and printable devices. In an embodiment, for example,the printable semiconductor elements comprise on or more printablecomponents of a device selected from the group consisting of anelectronic device, an array of electronic device, an optical device, anelectro-optical device, a microfluidic device, a microelectromechanicalsystem, a nanoelectromechanical system, a sensor, an integrated circuit,a microprocessor, and a memory device.

In specific methods, at least of portion of the heterogeneoussemiconductor elements comprise one or more printable semiconductordevices selected from the group consisting of a diode, a transistor, aphotovoltaic cell, a light emitting diode, a laser, a P-N junction, athin film transistor, a high electron mobility transistor, a photodiode,a metal-oxide-semiconductor field-effect transistor, ametal-semiconductor field effect transistor, a photodetector, a logicgate device, and a vertical-cavity surface-emitting laser. In anembodiment, for example, at least of portion of the printablesemiconductor devices are assembled on the substrate via contactprinting such that the printable semiconductor devices are provided inelectrical contact with electrodes pre-patterned on the substrate.

Methods of the present invention may further comprise multiple, andoptionally iterative, steps of assembling printable semiconductorelements on a substrate or structure(s) provided thereon, such as devicecomponent structures, interlayer structure and/or planarizing orencapsulating layers. In an embodiment, for example, a method of thepresent invention further comprises the step of assembling additionalprintable semiconductor elements on the substrate by contact printingthe additional printable semiconductor elements onto the semiconductorelements provided on the receiving surface of the substrate or onto oneor more intermediate structures provided between the semiconductorelements provided on the receiving surface of the substrate and theadditional printable semiconductor elements, thereby generating amultilayer device structure.

A multilayer device structure fabricated by the present methods maycomprise a plurality of device layers separated by one or moreinterlayers; wherein the device layers comprise printable semiconductorelements. In some embodiments, for example, the device layers havethicknesses less than or equal to 1 micron and wherein the interlayershave thicknesses less than or equal to 1.5 microns. In some embodiments,methods of this aspect further comprise the step of establishingelectrical contact between printable semiconductors provided indifferent device layers.

A specific method of this aspect further comprises the steps of: (i)providing an interlayer on top of the printable semiconductor elementsprinted onto the receiving surface of the substrate or the one or morestructures provided thereon; and (ii) assembling the additionalprintable semiconductor elements by contact printing the printablesemiconductor elements onto a receiving surface of the interlayer. In anembodiment, for example, at least a portion of the additional printablesemiconductor elements provided on the receiving surface of theinterlayer are positioned such that they are spatially aligned, inelectrical contact or both with the printable semiconductor elementsprovided on the receiving surface of the substrate. Methods of thisaspect may optionally further comprise the steps of: (i) patterning oneor more openings in the interlayer, thereby exposing regions of one ormore of the printable semiconductor elements provided on the receivingsurface of the substrate or the one or more structures provided thereon;and (ii) establishing electrical contact through the openings in theinterlayer between printable semiconductor elements provided on thereceiving surface of the substrate or the one or more structuresprovided thereon and the semiconductor elements provided on thereceiving surface of the interlayer.

Methods of the present invention may include an number of optionalprocessing steps. A method of the present invention further comprisesthe step of providing an adhesive layer on the receiving surface,wherein the printable semiconductor elements are printed onto theadhesive layer. A method of the present invention further comprises thestep of providing an encapsulating layer or planarizing layer on theprintable semiconductor elements printed onto the receiving surface ofthe substrate or the one or more structures provided thereon. A methodof the present invention further comprises the step of patterning thereceiving surface of the substrate or one or more printablesemiconductor elements printed onto the receiving surface of thesubstrate or the one or more structures provided thereon with one ormore thin films of conducting material via a deposition method. Methodsof the present invention are applicable to a range of substratesincluding, but not limited to, flexible substrates; polymer substrates,plastic substrates, stretchable substrates; rigid substrates;semiconductor wafers and a contoured substrate.

The invention also includes devices and systems made using the presentmethods. Devices and systems of the present invention include, but arenot limited to, electronic devices, optical devices, electro-opticaldevices, microfluidic devices, microelectromechanical systems,nanoelectromechanical systems, sensors, integrated circuits,microprocessors, and memory devices.

In another embodiment, the invention is a two-dimensional stretchableand bendable device. In this aspect, the device comprises a substratehaving a contact surface, where a component is bonded to at least aportion of the substrate contact surface, wherein the component has atleast one relief feature region and at least one substantially flatregion; wherein the relief feature region has a portion that isseparated from the substrate, and the substantially flat region is atleast partially bonded to the substrate. In an aspect, the at least onerelief feature region has a two-dimensional pattern of relief featureson the substrate, such as a wavy pattern having a plurality of contactregions in contact with the substrate contact surface.

To facilitate bonding of the component to the substrate, any one or bothof the component or substrate receiving surface may have activatedregions, such as a pattern of activated regions. “Active regions” isused broadly to refer to means for bonding and/or means for providingbuckling, such as by on or more of a pattern of adhesive sites on saidsubstrate contact surface or said component; a selected pattern ofsubstrate or component physical parameters, said parameter selected fromone or more of: substrate or component thickness, modulus, temperature,composition, each having a spatial variation; chemical modification ofthe substrate surface; and regions adjacent to free edges of thecomponent on the substrate contact surface. The common theme for each ofthese parameters is that they either facilitate bonding between thecomponent and substrate or provide a mechanism for generatingspatially-controlled buckling of the component. For example, positioningthe substantially flat region or a portion of the relief feature regionto an active substrate region, the component may be controllably buckledto provide for stretchable components.

Any of the devices and methods disclosed herein optionally have acomponent selected from the group consisting of one or more of: a metal,a semiconductor, an insulator, a piezoelectric, a ferroelectric, amagnetostrictive material, an electrostrictive material, asuperconductor, a ferromagnetic material, and a thermoelectric material.Any of the devices and methods disclosed herein is optionally for adevice selected from the group consisting of an electronic device, anoptical device, an opto-electronic device, mechanical device, and athermal device.

In an aspect, any of the two dimensional stretchable and bendabledevices have a substantially flat region comprising an island forreceiving a device component, such as an interconnect relief featurethat electrically connects at least two islands.

In an embodiment, any of the substrate contact or receiving surface is:flat, substantially flat, has a relief feature, has a curved portion,has a wavy portion, or is elastomeric, such as a PDMS substrate orsubstrate layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 summarizes one method for making a wavy or buckled stretchablemetal interconnect. A is a flow-chart summary and B illustrates theflow-chart steps.

FIG. 2 is a photograph of a stretchable wavy/buckled electricalinterconnect, formed by retrieval from a rigid substrate onto apre-strained, stretchable PDMS rubber substrate followed by the releaseof the strain to induce buckling.

FIG. 3 summarizes one method of fabrication of wavy stretchableelectrodes by deposition on a wavy-structured elastomer substrate.

FIG. 4 provides details relating to one method for fabricating a smoothwavy elastomer substrate. A is a flow-chart summary and B illustratesthe flow-chart steps.

FIG. 5 provides an image of a smoothly wavy PDMS substrate generated bythe methods outlined in FIGS. 3-4. The interconnect shown is capable of22.6% stretchability and has a metal interconnect that is about 900 nmthick (700 nm Al/200 nm Au), a wavelength of about 38 microns and anamplitude (distance from peak to valley) of about 15.6 microns. B showsone end of the interconnect for establishing electrical contact with adevice component. The device component may be positioned in a flatportion of the substrate.

FIG. 6A Commercially available lenticular array (from Edmund Optics)with cusps. B. Spin-coat photocurable epoxy to make smoothly wavysubstrate. C. Cast PDMS stamp against substrate from B to generate wavyelastomer stamp with smooth features.

FIG. 7 Stretchable electrodes deposited by evaporation through ashadowmask onto a smoothly wavy elastomer substrate. The electrodesmaintain conductivity and connectivity during stretching up to ˜10% intension. The scale bar is about 0.1 mm. A is a cross-section of wavinesson an elastomeric substrate. B is a top view micrograph of electrodeevaporated onto the wavy elastomer substrate. The focal plane is on thepeaks of the wavy relief. C is a top view micrograph of an electrodeevaporated onto the wavy elastomer substrate. The focal plane is on thevalleys of the wavy relief.

FIG. 8 is a schematic illustration of a process for the fabrication of astretchable passive matrix LED display using stretchable electrodes.

FIG. 9 illustrates the mechanical stretchability of a passive matrix LEDdisplay with wavy electrodes.

FIG. 10 illustrates inorganic photodiode arrays distributed on a lenswith spherical curvature. Shown: various lens shapes and angles

FIG. 11 illustrates the need for stretchability when a planar sheet iswrapped around a spherical surface.

FIG. 12 summarizes one scheme for fabricating stretchable buckledsemiconductor arrays capable of conforming to spherically-curvedsurfaces.

FIG. 13 Optical microscopic images of buckled stretchable silicon arrayshaving a single connection grid configuration (A and B), multipleconnection (e.g., two) grid configuration (C), and a floral connectionconfiguration (D). The stretchable interconnects are capable ofelectrically connecting photodiode, light-collecting/detecting devices,and other device components at, for example, the contact pad regions.These systems are capable of conforming to a curved surface. Theconfigurations depicted in FIG. 13A-D are on a PDMS substrate.

FIG. 14 Electron microscopic images of buckled stretchable siliconarrays in a grid configuration capable of supporting device componentsand conforming to a curved surface. The scale bar is 200 μm in A and 50μm in B.

FIG. 15 Electron microscopic images of buckled stretchable siliconarrays in a grid configuration with adjacent contact pads connected toone another by a plurality (e.g., two) of interconnects and capable ofsupporting device components and conforming to a curved surface. Thescale bar is 200 μm in A and 50 μm in B.

FIG. 16 Electron microscopic images of buckled stretchable siliconarrays in a floral configuration capable of supporting device componentsand conforming to a curved surface. The scale bar is 200 μm in A and 50μm in B.

FIG. 17 Electron microscopic images of buckled stretchable siliconarrays in a bridge configuration capable of supporting device componentsand conforming to a curved surface. The scale bar is 200 μm in A and 50μm in B.

FIG. 18 Photograph of photodiodes in a grid array configuration on astretchable buckled silicon array on PDMS.

FIG. 19 demonstrates the reversible behavior of the stretchableinterconnects during stretching and relaxation. The system is relaxed inpanel 1. The system is stretched as indicated by the stretching arrowsin panels 2, 3 and 4. The maximum stretch in panel 4 is about 10% andresults in a substantially flat interconnect for the interconnectaligned in the direction of the stretching force. The system is releasedin panels 5-8, and panel 8 has a geometry and configuration equivalentto that shown in panel 1. The scale bar is 0.2 mm.

FIG. 20 “Bubble stamp” or “Balloon stamp” device capable of conformalcontact to curved substrates as well as flat substrates.

FIG. 21 Another device capable of conforming to both spherically curvedand flat surfaces is a stretchable spherically-molded stamp. The stampis cast against a curved surface (in this example a concave lens) andremoved. The stamp is stretched to substantially flatten its surface andto which interconnects can be transferred.

FIG. 22 Stretchable buckled silicon arrays during a stretching cycle ona “bubble” or “balloon” stamp. In this example the interconnect betweenadjacent contact pads comprises two wavy interconnects (Si 290 nm inthickness). The stretch test uses bubble expansion to providemulti-directional stretching. The right-most panel is under maximumstretch and the bottom two panels show that when the stretching force isremoved, the interconnects relax back to their prestretchedconfiguration shown in the top-left panel.

FIG. 23 Silicon printed via balloon stamps onto glass lenses coated withadhesives (PDMS or SU-8).

FIG. 24 summarizes processing steps for engineering 3D buckled shapes insemiconductor nanoribbons. A Fabricating a UVO mask and using it topattern the surface chemistry on a PDMS substrate. B Forming buckledGaAs ribbons and embedding them in PDMS. C Response of buckled GaAsribbons to stretching and compressing. D SEM image of a sample formedusing the procedures in a and b. The prestrain used for generating thissample was 60%, with W_(act)=10 μm and W_(in)=400 μm.

FIG. 25 Side-view profiles of buckles formed on PDMS substrates usingprestrains of 33.7% and with: (A) W_(act)=10 μm and W_(in)=190 μm; and(B) W_(act)=100 μm and W_(in)=100 μm. Both samples exhibit buckles inthe inactivated regions due to detachment of ribbons from the PDMS.Sinusoidal waves with small peaks formed only in the activated regionswith W_(act)=100 μm. A comparison of these two samples indicates thatselecting W_(act) smaller than a critical value avoids the formation ofsmall wavy structures

FIG. 26 Side-view image of a buckled GaAs ribbon embedded in PDMS aftermicrotoming. This image shows that the PDMS fully fills the gaps betweenthe ribbons and the underlying substrate. The buckles in this case areformed with a prestrain of 60% and with W_(act)=10 μm and W_(in)=300 μm.The PDMS prepolymer cast on the surface of these buckled ribbons iscured in an oven at 65° C. for 4 hours.

FIG. 27 Optical micrographs of the side-view profiles of buckled (A andD) GaAs and (B, C) Si ribbons. A GaAs ribbon structures formed on PDMSpatterned with W_(act)=10 μm and W_(in)=190 μm, with differentprestrains: 11.3%, 25.5%, 33.7%, and 56.0% (from top to bottom). Thedotted lines for ∈_(pre)=33.7% and 56.0% are mathematically predictedinterconnect geometrical shape. B Si ribbon structures formed on a PDMSsubstrate prestrained to 50% and patterned with W_(act)=15 μm andW_(in): 350, 300, 250, 250, 300, and 350 μm (from left to right). Theimage was taken by tilting the sample at angle of 45°. C Si ribbonstructures formed on a PDMS substrate prestrained to 50% and patternedwith parallel lines of adhesion sites (W_(act)=15 μm and W_(in)=250 μm)orientated at angles of 30° with respect to the lengths of the ribbons.The image was taken by tilting the sample at angle of 75°. D GaAs ribbonstructures formed on PDMS substrates prestrained to 60% with W_(act)=10μm and different W_(in): 100, 200, 300, and 400 μm (from top to bottom).

FIG. 28 Stretching and compressing of buckled GaAs ribbons embedded inPDMS. A Images of a single buckled ribbon stretched to different levelsof tensile strain (positive %). Fracture occurs near 50%. B Images of asingle buckled ribbon compressed to different levels of compressivestrain (negative %). Small, short period wavy geometries appear at thepeaks of the buckles for compressive strains larger than ˜−15%. C Imagesof a single buckled ribbon compressed to different levels of compressivestrain. The buckles in these cases were formed with prestrain of 60%with W_(act)=10 μm and W_(in)=400 μm (A, B) and with W_(act)=10 μm andW_(in)=300 μm (C). The red lines and arrows in each panel indicate thesame positions on the same ribbons to highlight the mechanicaldeformations. The insets provide magnified images of the sections markedwith the white boxes, clearly showing the formation of cracks at highcompressive strains. The numbers corresponding to stretching orcompressing degree were computed according to:

${\frac{L_{projected}^{\max} - L_{projected}^{0}}{L_{projected}^{0}}}*100\%$

FIG. 29 Photograph of a sample with two layer of buckled GaAs ribbonsarrays. The structure is fabricated in a layer by layer scheme. Thefirst layer of GaAs ribbons (buckled geometry defined with a prestrainof 60% and with W_(act)=10 μm and W_(in)=400 μm) is embedded in PDMS.The second layer of buckled ribbons is formed on the surface of thissubstrate using a prestrain of 50% and with W_(act)=10 μm and W_(in)=300μm.

FIG. 30 Bending of buckled ribbons on surfaces and in matrixes of PDMS.A-C, Optical microscopic images with low magnification (top left frames)and high magnification (right frames) and schematic illustrations(bottom left frames) of buckled GaAs ribbons on PDMS with (A) concave,(B) flat, and (C) convex surfaces. The scale bars in c apply to a and b.d, Images of buckled ribbons embedded in PDMS (left) before and (right)after bending. The top and bottom frames show the curvatures of the topand bottom surfaces, respectively. The scale bars in the right imagesapply also to the left images. The buckled ribbons are formed with apre-strain of 60% and with W_(act)=10 μm and W_(in)=400 μm.

FIG. 31 Characterization of stretchable metal-semiconductor-metalphotodetectors (MSM PDs). A Schematic illustrations of the geometry(top), an equivalent circuit (middle), and optical images of a buckledPD before and during stretching (bottom). B Current (I)-voltage (V)curves recorded from a buckled PD that was irradiated by an IR lamp withdifferent output intensities. I-V characteristics of PDs illuminatedwith constant luminance and (C) stretched or (D) compressed by differentdegrees.

FIG. 32 A hemispherical elastomeric transfer ‘stamp’ can liftoffinterconnected Si CMOS ‘chiplets’ from a conventional wafer and thentransform their geometry into a hemispherical shape. The ‘pop-up’interconnects between the chiplets accommodates the strains associatedwith this planar to curved surface transformation.

FIG. 33 Transfer of interconnected CMOS chiplets from a hemisphericalstamp to a matched hemispherical device substrate. The photocurableadhesive layer bonds to the CMOS to the device substrate and alsoplanarizes the surface.

FIG. 34 Printer apparatus with fixturing, actuators and vision systemscompatible with hemispherical stamps.

FIG. 35 Compressible array of single crystal silicon islandselectrically connected by ‘pop up’ ribbon interconnects, on ahemispherical stamp.

FIG. 36 Optical images of an array of interconnected single crystalsilicon islands ‘inked’ onto the surface of a hemispherical stamp withradius of curvature ˜2 cm.

FIG. 37 Stress/strain curves for various silicone elastomers that can beused for the hemispherical stamps. Linear, purely elastic responses forstrains less than 20% are important.

FIG. 38 Finite element modeling of the spherical to planartransformation in a hemispherical stamp with an initially uniformthickness of 0.57 mm.

FIG. 39 Schematic illustration of steps for fabricating two-dimensional,“wavy” semiconductor nanomembranes on elastomeric supports.

FIG. 40 (a-f) Optical micrographs of 2D wavy structures in siliconnanomembranes at various stages during their formation. The insets showtwo-dimensional power spectra. (g) Image of the fully developedstructure, at low magnification. For this sample, the thickness of thesilicon is 100 nm with the lateral dimension of ca. 4×4 mm², thesubstrate is PDMS, and the thermally induced prestrain is 3.8%. (h) Plotof the short wavelength corresponding to frames (a-f) and (i) histogramof long wavelength evaluated at various points from frame (g).

FIG. 41 (a) AFM and (b-d) SEM images (tilt angle) 60°) of a 2D wavy Sinanomembrane on PDMS. The thickness of the silicon is 100 nm, and thethermal prestrain is 3.8%. These images highlight the highly periodicnature of the wavy patterns, the good bonding between the Si and thePDMS as evidenced by the intimate contact visible at the edges of the Siand PDMS near the holes etched in the Si, and the lack of correlationbetween the positions of the wave structures and these holes.

FIG. 42 (a) Optical micrographs of 2D wavy Si nanomembranes with variousthickness (55, 100, 260, 320 nm) on PDMS, formed with a thermalprestrain of 3.8%, and (b) dependence of the short wavelength andamplitude on Si thickness.

FIG. 43 (a) Optical micrographs of 2D wavy Si nanomembranes underdifferent uniaxial strains, applied at three different orientations.These samples consist of Si membranes with thicknesses of 100 nm onPDMS, formed with a thermal prestrain of 3.8%. The images were collectedin the relaxed state before stretching (top frames), the relaxed stateafter stretching (bottom frames), and at uniaxial applied tensilestrains of 1.8% (top middle frames) and 3.8% (bottom middle frames). (b)Dependence of the short wavelength on applied strain in the threedifferent directions.

FIG. 44 AFM images of different regions of a 2D wavy Si nanomembrane,showing the 1D wavy geometry characteristics of a region near the edgeof the membrane (top frame), a region slightly removed from this edgearea (middle frame), and a region near the center of the membrane(bottom frame). The sample consisted of a Si membrane with thickness of100 nm on PDMS, formed with a thermal prestrain of 3.8%.

FIG. 45 Optical micrographs of 2D wavy Si nanomembranes with lengths of1000 μm and with widths of 100, 200, 500, and 1000 μm. These membranesall have thicknesses of 100 nm and were formed on the same PDMSsubstrate with thermal prestrains of (a) 2.3% and (b) 4.8%. (c)Dependence of the edge effect length on prestrain for similar membranes.

FIG. 46 Optical micrographs of 2D wavy Si nanomembranes with differentshapes: (a) circle, (b) oval, (c) hexagon, and (d) triangle. Thesemembranes all have thicknesses of 100 nm and were formed on PDMS with athermal prestrain of 4.8%.

FIG. 47 Optical micrographs of wavy structures of Si nanomembranes withshapes designed to exploit edge effects to provide 2D stretchability ininterconnected arrays of flat islands. In both cases illustrated here,the Si is 100 nm thick, the squares are 100×100 μm and the ribbonconnections are 30×150 μm lines. The prestrain is (a, e) 2.3% and (c, g)15%. SEM images (tilt angle of 75°) of selected regions that showribbons and squares of (a, c, e, g) are shown in (b, d, f, h),respectively. The insets of high-magnification SEM images show theraised region of waves in b and d.

FIG. 48 is photograph of the sample of 2D wavy Si nanomembrane (100 nmthick, 4×5 mm², and 3.8% thermal prestrain) on PDMS substrate wave (topframe), and (i) the 1D waves at the edge, (ii) the herringbone waves atthe inner region, and (iii) disordered herringbone waves at the center.The scale bar is 50 μm.

FIG. 49 Schematic illustration of the characteristic lengths in theherringbone wave structures.

FIG. 50 Si strain as a function of applied thermal prestrain at theherringbone and 1D waves. Si strain was measured experimentally by∈_(Si)=(L−λ)/λ, where L and λ are the surface and horizontal distance inAFM surface profile.

FIG. 51 Optical microscope images of herringbone waves after the cyclesof stretching test (˜∈_(st)=4.0%). The test sample was prepared with 100nm thick Si membrane and 3.8% biaxial thermal prestrain. The herringbonewaves were recovered to have quite similar structures with the original,after the cycles of stretching test up to 15 times, except the somedefects originated from the crack of membrane.

FIG. 52 Schematic illustration of the ‘unfolding’ of herringbone waveswith application of uniaxial tensile strain. The compressive strain∈_(cp) is due to the Poisson effect with tensile strain ∈_(st).

FIG. 53 Optical microscope images of the morphology change ofherringbone waves during heating and cooling process as a biaxialstretching test. The test sample was prepared with 100 nm thick Simembrane and 2.9% biaxial thermal prestrain.

FIG. 54 summarizes one method of fabrication of wavy stretchableelectrodes by deposition on a structured wavy master, followed bycasting a stamp on that master, curing the stamp, and therebytransferring the electrodes to the master upon release.

FIG. 55 provides an image of stretchable metal electrodes (Au, 300 nmthick) on wavy PDMS prepared by the methods in FIG. 4 combined withthose in FIG. 54. The bottom panel is a graph of measured electricalresistance data of the stretchable wavy metal electrodes as a functionof applied tensile strain (up to 30%).

FIG. 56 is an example of an application of the present method for makingflexible, stretchable iLED strip-lights. A is a photomicrographillustrating the device is capable of large bending, and in this examplethe bending radius is 0.85 cm. B provides a cross-section (top panel,scale bar 40 μm) and a top-view (bottom panel, scale bar 3 mm) ofstretchable metal on a wavy PDMS substrate. The metal is capable ofstretching about 30% without significant degradation of physicalproperties. C is a plot of the effects of local strain on the wavelength(squares, left axis) and amplitude (circles, right axis) ofsinusoidally-wavy metal interconnects on PDMS (shown in B). As thestrain increases, there is a corresponding increase in the wavelengthand decrease in the amplitude of the metal.

FIG. 57 Schematic illustration of a printed semiconductor nanomaterialsbased approach to heterogeneous, three dimensional electronics. Theprocess involves the repetitive transfer printing of collections ofnanotubes, nanowires, nanoribbons or other active nanomaterials,separately formed on source substrates, to a common device substrate togenerate interconnected electronics in ultrathin, multilayer stackgeometries.

FIG. 58 (A) Optical micrograph of a three dimensional multilayer stackof arrays of single crystal silicon metal oxide field effect transistors(MOSFETs) that use printed silicon nanoribbons for the semiconductor.The bottom (labeled 1st), middle (labeled 2nd) and top (labeled 3rd)parts of this image correspond to regions with one, two and three layersof devices, respectively. (B) Schematic cross sectional (top) and angled(bottom) views. S, D and G refer to source, drain and gate electrodes(all shown in gold), respectively. The light and dark blue regionscorrespond to doped and undoped regions of the silicon ribbons; thepurple layer is the SiO₂ gate dielectric. (C) Three dimensional images(left frame: top view; right frame: angled view) collected by confocalmicroscopy on a device substrate like that shown in (A) and (B). Thelayers are colorized (gold: top layer; red: middle layer; blue: bottomlayer; silicon: grey) for ease of viewing. (D) Current-voltagecharacteristics of Si MOSFETs in each of the layers, showing excellentperformance (mobilities of 470±30 cm²/Vs) and good uniformity in theproperties. The channel lengths and widths are 19 and 200 μm,respectively.

FIG. 59 (A) Optical micrograph of three dimensional, heterogeneouslyintegrated electronic devices, including GaN nanoribbon HEMTs, Sinanoribbon MOSFETs and SWNT network TFTs, in a three layer stack. (B)Three dimensional image collected by confocal microscopy. The layers arecolorized (gold: top layer, Si MOSFETs; red: middle layer, SWNT TFTs;blue: bottom layer) for ease of viewing. (C) Electrical characteristicsof GaN devices on the first layer (channel lengths, widths and gatewidths of 20, 170 and 5 μm, respectively), SWNT devices on the secondlayer (channel lengths and widths of 50 and 200 μm, respectively) and Sidevices on the third layer (channel lengths and widths of 19 and 200 μm,respectively). (D) Normalized transconductances (g_(m)/g_(0m)) ofdevices in each layer (black squares: Si MOSFETs; red circles: SWNTTFTs; green triangles: GaN HEMTs) as a function of bending radius of theplastic substrate (left). Image of the bent system and probing apparatus(right).

FIG. 60 (A) Image of a printed array of 3D silicon NMOS inverters on apolyimide substrate. The inverters consist of MOSFETs (channel lengthsof 4 μm, load-to-driver width ratio of 6.7, and a driver width of 200μm) on two different levels, interconnected by electrical viastructures. The image on the top right provides a magnified view of theregion indicated by the red box in the left frame. The graph on thebottom right shows transfer characteristics of a typical inverter. (B)Transfer characteristics of a printed complementary inverter that uses ap channel SWNT TFT (channel length and width of 30 and 200 μm,respectively) and an n channel Si MOSFET (channel length and width of 75and 50 μm, respectively). The insets provide an optical micrograph of aninverter (left) and a circuit schematic (right). (C) Current-voltageresponse of a GaAs MSM (channel length and width of 10 and 100 μm,respectively) integrated with a Si MOSFET (channel length and width of 9and 200 μm, respectively) at different levels of illumination from darkto 11 μW with an infrared light source at 850 nm. The insets shows andoptical image, and a circuit diagram.

FIG. 61 Image of an automated stage for transfer-printing, capable ofregistration to within ˜1 μm.

FIG. 62 (A) Optical micrographs of three dimensional, heterogeneouslyintegrated arrays of Si MOSFETs and GaN HEMTs on a polyimide substrate.The right inset shows a cross sectional schematic view. The electrodes(gold), SiO₂ (PEO; purple), Si (light blue: undoped; dark blue: doped),GaN (dark green: ohmic contacts; light green: channel), polyimide (PI;brown) and polyurethane (PU; tan) are all shown. (B) Current-voltagecharacteristics of a typical Si MOSFET (channel length and width of 19and 200 μm, respectively) and a GaN HEMT with (channel length, widthsand gate widths of 20, 170 μm and 5 μm, respectively). The data for theSi and GaN in the left frames were measured at V_(dd)=0.1V andV_(dd)=2V, respectively.

FIG. 63 (A) Optical micrographs of three dimensional, heterogeneouslyintegrated arrays of Si MOSFETs and SWNT TFTs on a polyimide substrate.The right inset shows a cross sectional schematic view. The electrodes(gold), epoxy (cyan), SiO2 (PEO; purple), Si (light blue: undoped; darkblue: doped), SWNTs (grey), polyimide (PI; brown) and cured polyimide(tan) are all shown. (B) Current-voltage characteristics of a typicalSWNT TFT (channel length and width of 75 μm and 200 μm, respectively)and a typical Si MOSFET (gate length and channel width 19 μm and 200 μm,respectively). The data for the SWNT and Si in the left frames weremeasured at V_(dd)=−0.5 V and V_(dd)=0.1 V, respectively.

FIG. 64 (A) Cross sectional schematic illustration of three dimensional,heterogeneously integrated arrays of Si MOSFETs, SWNT TFTs and GaN HEMTson a polyimide substrate. (B) Transfer characteristics, effectivemobilities and on/off ratios for several of the Si MOSFETs (channelwidth=200 μm, black line: channel length=9 μm, red: 14 μm, green: 19 μm,blue: 24 μm), (C) the SWNT TFTs (channel width=200 μm, black line:channel length=25 μm, red: 50 μm, green: 75 μm, blue: 100 μm) and (D)transfer characteristics, transconductances and on/off ratios for GaNHEMTs (channel lengths, widths and gate widths of 20 μm, 170 μm and 5μm, respectively).

FIG. 65 (A) Schematic structure of the cross section of SWNT-Si CMOSinverter built on a silicon wafer substrate. (B) Transfer and I-Vcharacteristics of n-channel Si MOSFET and p-channel SWNT TFT formingCMOS inverter. (C) Calculated transfer characteristics of inverter andI-V characteristics of Si and SWNT transistors.

FIG. 66 (A) Schematic structure of the cross section and circuitschematic of GaAs MSM-Si MOSFET IR detector built on a polyimidesubstrate. (B) Current-Voltage characteristic of GaAs MSM IR detector(L=10 μm, W=100 μm) and transfer and I-V characteristics of Si MOSFET(L=9 μm, W=200 μm) with a 3V supply. (C) Calculated IV characteristic ofGaAs MSM and I-V response of a GaAs MSM integrated with a Si MOSFET witha 3V supply.

FIG. 67 schematically illustrates an optical device (waveguide array)produced via the controlled buckling of an optical microstructurepartially adhered to a deformable substrate.

FIG. 68 schematically illustrates a mechanical device (e.g.,accelerometer/pressure sensor) produced via the controlled buckling of aconductive microstructure partially adhered to a deformable substrate.

FIG. 69 schematically illustrates a thermal device (microbolometer)produced via the controlled buckling of a thermoresistive microstructurepartially adhered to a deformable substrate.

DETAILED DESCRIPTION OF THE INVENTION

“Stretchable” refers to the ability of a material, structure, device ordevice component to be strained without undergoing fracture. In anexemplary embodiment, a stretchable material, structure, device ordevice component may undergo strain larger than about 0.5% withoutfracturing, preferably for some applications strain larger than about 1%without fracturing and more preferably for some applications strainlarger than about 3% without fracturing.

A “component” is used broadly to refer to a material or individualcomponent used in a device. An “interconnect” is one example of acomponent and refers to an electrically conducting material capable ofestablishing an electrical connection with a component or betweencomponents. In particular, the interconnect may establish electricalcontact between components that are separate and/or can move withrespect to each other. Depending on the desired device specifications,operation, and application, the interconnect is made from a suitablematerial. For applications where a high conductivity is required,typical interconnect metals may be used, including but not limited tocopper, silver, gold, aluminum and the like, alloys. Suitable conductivematerials may include a semiconductor like silicon, indium tin oxide, orGaAs.

“Semiconductor” refers to any material that is an insulator at a verylow temperature, but which has a appreciable electrical conductivity ata temperatures of about 300 Kelvin. In the present description, use ofthe term semiconductor is intended to be consistent with use of thisterm in the art of microelectronics and electronic devices.Semiconductors useful in the present invention may comprise elementsemiconductors, such as silicon, germanium and diamond, and compoundsemiconductors, such as group IV compound semiconductors such as SiC andSiGe, group III-V semiconductors such as AlSb, AlAs, Aln, AlP, BN, GaSb,GaAs, GaN, GaP, InSb, InAs, InN, and InP, group III-V ternarysemiconductors alloys such as Al_(x)Ga_(1-x)As, group II-VIsemiconductors such as CsSe, CdS, CdTe, ZnO, ZnSe, ZnS, and ZnTe, groupI-VII semiconductors CuCl, group IV-VI semiconductors such as PbS, PbTeand SnS, layer semiconductors such as PbI₂, MoS₂ and GaSe, oxidesemiconductors such as CuO and Cu₂O. The term semiconductor includesintrinsic semiconductors and extrinsic semiconductors that are dopedwith one or more selected materials, including semiconductor havingp-type doping materials and n-type doping materials, to providebeneficial electronic properties useful for a given application ordevice. The term semiconductor includes composite materials comprising amixture of semiconductors and/or dopants. Specific semiconductormaterials useful for in some applications of the present inventioninclude, but are not limited to, Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP,GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe, CdS,CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs,AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, and GaInAsP. Poroussilicon semiconductor materials are useful for applications of thepresent invention in the field of sensors and light emitting materials,such as light emitting diodes (LEDs) and solid state lasers. Impuritiesof semiconductor materials are atoms, elements, ions and/or moleculesother than the semiconductor material(s) themselves or any dopantsprovided to the semiconductor material. Impurities are undesirablematerials present in semiconductor materials which may negatively impactthe electronic properties of semiconductor materials, and include butare not limited to oxygen, carbon, and metals including heavy metals.Heavy metal impurities include, but are not limited to, the group ofelements between copper and lead on the periodic table, calcium, sodium,and all ions, compounds and/or complexes thereof.

“Semiconductor element” and “semiconductor structure” are usedsynonymously in the present description and broadly refer to anysemiconductor material, composition or structure, and expressly includeshigh quality single crystalline and polycrystalline semiconductors,semiconductor materials fabricated via high temperature processing,doped semiconductor materials, organic and inorganic semiconductors andcomposite semiconductor materials and structures having one or moreadditional semiconductor components and/or non-semiconductor components,such as dielectric layers or materials and/or conducting layers ormaterials

An interconnect that is “stretchable” is used herein to broadly refer toan interconnect capable of undergoing a variety of forces and strainssuch as stretching, bending and/or compression in one or more directionswithout adversely impacting electrical connection to, or electricalconduction from, a device component. Accordingly, a stretchableinterconnect may be formed of a relatively brittle material, such asGaAs, yet remain capable of continued function even when exposed to asignificant deformatory force (e.g., stretching, bending, compression)due to the interconnect's geometrical configuration. In an exemplaryembodiment, a stretchable interconnect may undergo strain larger thanabout 1%, 10% or about 30% without fracturing. In an example, the strainis generated by stretching an underlying elastomeric substrate to whichat least a portion of the interconnect is bonded.

A “device component” is used to broadly refer to an individual componentwithin an electrical, optical, mechanical or thermal device. Componentcan be one or more of a photodiode, LED, TFT, electrode, semiconductor,other light-collecting/detecting components, transistor, integratedcircuit, contact pad capable of receiving a device component, thin filmdevices, circuit elements, control elements, microprocessors,transducers and combinations thereof. A device component can beconnected to one or more contact pads as known in the art, such as metalevaporation, wire bonding, application of solids or conductive pastes,for example. Electrical device generally refers to a deviceincorporating a plurality of device components, and includes large areaelectronics, printed wire boards, integrated circuits, device componentsarrays, biological and/or chemical sensors, physical sensors (e.g.,temperature, light, radiation, etc.), solar cell or photovoltaic arrays,display arrays, optical collectors, systems and displays.

“Substrate” refers to a material having a surface that is capable ofsupporting a component, including a device component or an interconnect.An interconnect that is “bonded” to the substrate refers to a portion ofthe interconnect in physical contact with the substrate and unable tosubstantially move relative to the substrate surface to which it isbonded. Unbonded portions, in contrast, are capable of substantialmovement relative to the substrate. The unbonded portion of theinterconnect generally corresponds to that portion having a “bentconfiguration,” such as by strain-induced interconnect bending.

A component in “conformal contact” with a substrate refers to acomponent that covers a substrate and retains a three-dimensional relieffeature whose pattern is governed by the pattern of relief features onthe substrate.

In the context of this description, a “bent configuration” refers to astructure having a curved conformation resulting from the application ofa force. Bent structures in the present invention may have one or morefolded regions, convex regions, concave regions, and any combinationsthereof. Bent structures useful in the present invention, for example,may be provided in a coiled conformation, a wrinkled conformation, abuckled conformation and/or a wavy (i.e., wave-shaped) configuration.

Bent structures, such as stretchable bent interconnects, may be bondedto a flexible substrate, such as a polymer and/or elastic substrate, ina conformation wherein the bent structure is under strain. In someembodiments, the bent structure, such as a bent ribbon structure, isunder a strain equal to or less than about 30%, a strain equal to orless than about 10%, a strain equal to or less than about 5% and astrain equal to or less than about 1% in embodiments preferred for someapplications. In some embodiments, the bent structure, such as a bentribbon structure, is under a strain selected from the range of about0.5% to about 30%, a strain selected from the range of about 0.5% toabout 10%, a strain selected from the range of about 0.5% to about 5%.Alternatively, the stretchable bent interconnects may be bonded to asubstrate that is a substrate of a device component, including asubstrate that is itself not flexible. The substrate itself may beplanar, substantially planar, curved, have sharp edges, or anycombination thereof. Stretchable bent interconnects are available fortransferring to any one or more of these complex substrate surfaceshapes.

“Thermal contact” refers to the ability of two materials that arecapable of substantial heat transfer from the higher temperaturematerial to the lower temperature material, such as by conduction. Bentstructures resting on a substrate are of particular use in providingregions that are in thermal contact (e.g., bond regions) with thesubstrate and other regions that are not in thermal contact (e.g.,regions that are insulated and/or physically separated from thesubstrate).

Interconnects can have any number of geometries or shape, so long as thegeometry or shape facilitates interconnect bending or stretching withoutbreakage. A general interconnect geometry can be described as “buckled”or “wavy.” In an aspect, that geometry can be obtained by exerting aforce (e.g., a strain) on the interconnect by exerting a force on anunderlying deformable substrate, such that a change in a dimension ofthe underlying substrate generates buckles or waves in the interconnectbecause portions of the interconnect are bonded to the substrate, andregions between the bound portions are not bonded. Accordingly, anindividual interconnect may be defined by ends that are bonded to asubstrate, and a curved central portion between the ends that is notsubstrate-bonded. “Curved” or “buckled” refers to relatively complexshapes, such as by an interconnect having one or more additional bondregions in the central portion. “Arc-shaped” refers to a generallysinusoidal shape having an amplitude, where the amplitude corresponds tothe maximum separation distance between the interconnect and thesubstrate surface.

The interconnect can have any cross-sectional shape. One shapeinterconnect is a ribbon-shaped interconnect. “Ribbon” refers to asubstantially rectangular-shaped cross-section having a thickness and awidth. Specific dimensions depend on the desired conductivity throughthe interconnect, the composition of the interconnect and the number ofinterconnects electrically connecting adjacent device components. Forexample, an interconnect in a bridge configuration connecting adjacentcomponents may have different dimensions than a single interconnectconnecting adjacent components. Accordingly, the dimensions may be ofany suitable values, so long as a suitable electrical conductivity isgenerated, such as widths that are between about 10 μm and 1 cm andthickness between about 50 nm to 1, or a width to thickness ratioranging from between about 0.001 and 0.1, or a ratio that is about 0.01.

“Elastomeric” refers to a polymeric material which can be stretched ordeformed and return, at least partially, to its original shape withoutsubstantial permanent deformation. Elastomeric substrates commonlyundergo substantially elastic deformations. Exemplary elastomericsubstrates useful in the present include, but are not limited to,elastomers and composite materials or mixtures of elastomers, andpolymers and copolymers exhibiting elasticity. In some methods, theelastomeric substrate is prestrained via a mechanism providing forexpansion of the elastic substrate along one or more principle axes. Forexample, prestraining may be provided by expanding the elastic substratealong a first axes, including expansion in a radial direction totransform a hemispherical surface to a flat surface. Alternatively, theelastic substrate may be expanded along a plurality of axes, for examplevia expansion along first and second axis orthogonally positionedrelative to each other. Means of prestraining elastic substrates viamechanisms providing expansion of the elastic substrate include bending,rolling, flexing, flattening, expanding or otherwise deforming theelastic substrate. The prestraining means also includes prestrainingprovided by raising the temperature of the elastic substrate, therebyproviding for thermal expansion of the elastic substrate. Elastomersuseful in the present invention may include, but are not limited to,thermoplastic elastomers, styrenic materials, olefenic materials,polyolefin, polyurethane thermoplastic elastomers, polyamides, syntheticrubbers, PDMS, polybutadiene, polyisobutylene,poly(styrene-butadiene-styrene), polyurethanes, polychloroprene andsilicones.

Strain is defined as: ∈=ΔL/L for lengths changed from L (at rest) toL+ΔL (under an applied force), where ΔL is the displacement distancefrom resting. Axial strain refers to a force applied to an axis of thesubstrate to generate the displacement ΔL. Strain is also generated byforces applied in other directions, such as a bending force, acompressive force, a shearing force, and any combination thereof. Strainor compression may also be generated by stretching a curved surface to aflat surface, or vice versa. “Level of strain” refers to the magnitudeof the strain and can range from negative (corresponding to compression)to zero (relaxed state) to positive (corresponding to elongation orstretching).

“Young's modulus” is a mechanical property of a material, device orlayer which refers to the ratio of stress to strain for a givensubstance. Young's modulus may be provided by the expression;

$\begin{matrix}{{E = {\frac{({stress})}{({strain})} = \left( {\frac{L_{0}}{\Delta \; L} \times \frac{F}{A}} \right)}};} & ({II})\end{matrix}$

wherein E is Young's modulus, L₀ is the equilibrium length, ΔL is thelength change under the applied stress, F is the force applied and A isthe area over which the force is applied. Young's modulus may also beexpressed in terms of Lame constants via the equation:

$\begin{matrix}{{E = \frac{\mu \left( {{3\lambda} + {2\mu}} \right)}{\lambda + \mu}};} & ({III})\end{matrix}$

wherein λ and μ are Lame constants. High Young's modulus (or “highmodulus”) and low Young's modulus (or “low modulus”) are relativedescriptors of the magnitude of Young's modulus in a give material,layer or device. In the present invention, a high Young's modulus islarger than a low Young's modulus, preferably about 10 times larger forsome applications, more preferably about 100 times larger for otherapplications and even more preferably about 1000 times larger for yetother applications. Complex surface shapes are obtained by polymerizingan elastomer having a spatially-varying Young's modulus and/or bylayering an elastomer with multiple layers in various locations havingdifferent elasticity.

Compression is used herein in a manner similar to the strain, butspecifically refers to a force that acts to decrease a characteristiclength, or a volume, of a substrate, such that ΔL<0.

“Fracturing” or “fracture” refers to a physical break in theinterconnect, such that the interconnect is not capable of substantialelectrical conductivity.

A “pattern of bond sites” refers to spatial application of bonding meansto a supporting substrate surface and/or to the interconnects so that asupported interconnect has bond regions and non-bond regions with thesubstrate. For example, an interconnect that is bonded to the substrateat its ends and not bonded in a central portion. Further shape controlis possible by providing an additional bond site within a centralportion, so that the not-bonded region is divided into two distinctcentral portions. Bonding means can include adhesives, adhesiveprecursors, welds, photolithography, photocurable polymer. In general,bond sites can be patterned by a variety of techniques, and may bedescribed in terms of surface-activated (W_(act)) areas capable ofproviding strong adhesive forces between substrate and feature (e.g.,interconnect) and surface-inactive (W_(in)) where the adhesive forcesare relatively weak. A substrate that is adhesively patterned in linesmay be described in terms of W_(act) and W_(in) dimensions. Thosevariables, along with the magnitude of prestrain, ∈_(pre) affectinterconnect geometry.

“Spatial variation” refers to a parameter that has magnitude that variesover a surface, and is particularly useful for providing two-dimensionalcontrol of component relief features, thereby providing spatial controlover the bendability of a device or device component.

“Carbon nanomaterial” refers to a class of structures comprising carbonatoms and having at least one dimension that is between one nanometerand one micron. In an embodiment, at least one dimension of the carbonnanomaterial is between 2 nm and 1000 nm. Carbon nanomaterials includeallotropes of carbon such as single walled nanotubes (SWNTs),multiwalled nanotubes (MWNTs), nanorods, single walled and/ormultiwalled fullerenes, graphite, graphene, carbon fibers, carbon films,carbon whiskers, and diamond, and all derivatives thereof.

“Spatial aligned” refers to positions and/or orientations of two or morestructures that are defined with respect to each other. Spatiallyaligned structures may have positions and/or orientations that arepreselected with respect to each other, for example, preselected towithin 1 micron, preferably for some applications to within 500nanometers, and more preferably for some applications to within 50nanometers.

“Heterogeneous semiconductor elements” are multicomponent structurescomprising a semiconductor in combination with one or more othermaterials or structures. Other materials and structures in the contextof this description may comprise elements, molecules and complexes,aggregates and particles thereof, that are different from thesemiconductor in which they are combined, such as materials and/orstructures having a different chemical compositions and/or physicalstates (e.g. crystalline, semicrystalline or amorphous states). Usefulheterogeneous semiconductor elements in this aspect of the inventioninclude an inorganic semiconductor structure in combination with othersemiconductor materials, including doped semiconductors (e.g., N-typeand P-type dopants) and carbon nanomaterials or films thereof,dielectric materials and/or structures, and conducting materials and/orstructures. Heterogeneous semiconductor elements of the presentinvention include structures having spatial homogeneous compositions,such as uniformly doped semiconductor structures, and include structureshaving spatial inhomogeneous compositions, such as semiconductorstructures having dopants with concentrations that vary spatially inone, two or three dimensions (i.e. a spatially inhomogeneous dopantdistribution in the semiconductor element).

The invention may be further understood by the following non-limitingexamples. All references cited herein are hereby incorporated byreference to the extent not inconsistent with the disclosure herewith.Although the description herein contains many specificities, theseshould not be construed as limiting the scope of the invention but asmerely providing illustrations of some of the presently preferredembodiments of the invention. The scope of the invention should,therefore, be determined by the appended claims and their equivalents,rather than by the examples given.

One method for making buckled or wavy interconnects is generallysummarized in FIG. 1. A metal feature 10 (such as a metal feature thatwill be an interconnect) is provided on a substrate 20. The contactingmetal feature and/or substrate surfaces are optionally treated forreduced adhesion such as by photolithography or with a shadowmask. Aseparation (crack) 25 is introduced between the feature 10 and thesubstrate 20 such as by micromachining, etching and/or mechanicalscribing. The metal feature 10 is retrieved with a compliant elastomerstamp 30. Subsequent deformation of the stamp 30 generates in the metalfeature 10 a wavy or buckled geometry 40. Generation of the buckles isprovided by stamp 30 that is under strain when the metal feature 10 isretrieved and subsequently releasing the applied tension, or bycompressing stamp 30 after the metal feature is retrieved.

One example of a buckled or wavy metal feature generated by the methodsummarized in FIG. 1 is shown in FIG. 2. FIG. 2 is a photograph of astretchable wavy/buckled electrical interconnect 40, formed by retrievalfrom a rigid substrate onto a pre-strained, stretchable PDMS rubbersubstrate 30, followed by release of the strain, thereby inducingbuckling.

A method for generating wavy stretchable electrodes and/or interconnectsis provided in FIG. 3. As shown in FIG. 3A, wavy features 22 areprepared on a substrate 20, such as by micromachining processes, forexample. The substrate 20 with a surface having wavy features 22 servesas a master for molding elastomer stamps 30 with a corresponding wavysurface 32. Metal features 10 are deposited on the wavy surface 32, suchas by evaporation through a shadow mask and/or electrodeposition.

FIG. 4 provides one method for fabricating a smooth wavy elastomersubstrate. Anisotropic Si (1 0 0) etching provides a substrate 20 havingsharp-edges 24 (FIG. 4B—top panel). Spin PR smooths the sharp-edgedvalleys by depositing PR 26 in the sharp-edged valleys 24 of substrate20. An elastomeric stamp 34 is cast against substrate 20. Stamp 34 hassharp-edged recess features. A second elastomeric stamp 36 is cast onstamp 34 to generate a stamp having sharp-edged peaks. Stamp 36 isembossed with Su-8 50 and cured as appropriate. Spin PR 26 smooths thesharp-edged valleys of 50. Elastomeric substrate 30 is cast against the50 having smooth valleys. Substrate 30 is removed to reveal a wavy andsmooth surface 32.

FIG. 54 summarizes one method of fabrication of wavy stretchableelectrodes by deposition on a wavy master, followed by casting a stampon that master, curing the stamp, and thereby transferring theelectrodes to the master upon release. FIG. 55 shows images ofstretchable metal electrodes (Au, 300 nm thick) on wavy PDMS prepared bythe methods in FIG. 4 combined with those in FIG. 54. Interface 112 isshown between metal feature 10 and substrate 20. Interface 112 maycomprise material that facilitates removal of metal features 10 by stamp30 illustrated in the bottom panel. Briefly, one method uses: onpre-cleaned 2″×3″ glass slides, spin on a thin coating of SU-8 10 sothat glass surface is completely covered. Bring slide/SU-8 into contactwith PDMS stamp having the desired wavy surface features (smooth valleysand sharp peaks) and gently apply pressure so that all air pockets areremoved. Flash cure the stamp/mold structure under a UV lamp for 30seconds on the front side, flip, and cure for an additional 40 secondson the reverse side. After cure, bake on hot plate at 65° C. for 5minutes. After bake, allow sample to cool to room temperature and peelapart SU-8 mold from PDMS master. SU-8 will now have wavy surface reliefwith sharp edged valleys. To smooth out these valleys, mix one part SU-82 with one part SU-8 thinner, and spin on at high RPM for 90 seconds.Expose to UV light for 20 seconds to cure and post bake for 3 minutes at65° C. Once cool, metal lines or contacts are deposited viaelectrodeposition, photolithograph and etching/lift-off, and/orevaporation through a shadowmask. Treat the metal on SU-8 with MPTMS for1 hour and then cast elastomeric substrate against it. When removed, thePDMS has wavy surface relief with smoothed peaks and valleys along withtransferred metal structures. FIG. 55 is a photograph of the a wavystretchable electrode made by the process summarized in FIG. 54, andalso provides measured electrical resistance data of the stretchablewavy metal electrodes as a function of applied tensile strain (up to30%).

An example of a smoothly wavy PDMS substrate 30 made by the methodsummarized in FIG. 4 is provided in FIG. 5. A device component 60 can besupported to wavy substrate 30 in a non-wavy region (e.g., substantiallyflat portion) and connected to an interconnect 10 as desired.

An example of spin coating of a smoothing layer into a sharp-edgedvalley or recess feature is shown in FIG. 6. A sharp-edged substrate 34(FIG. 6A) is smoothed by spin-coating a photcurable epoxy 26 to generatea smoothly wavy substrate. An elastomer (e.g., PDMS) stamp 30 having asmoothly wavy surface 32 is obtained by casting a PDMS stamp against thesubstrate of FIG. 6B and subsequently removing the stamp 30 from thesubstrate 34.

FIG. 7 are photographs of a stretchable electrode. FIG. 7A is aphotograph of a cross-section of an elastomer substrate 30 having a wavysurface 32. FIG. 7B is a top view micrograph of an electrode made byevaporating metal 10 on the wavy elastomer substrate surface 32. Theimage's focal plane is on the peaks of the wavy relief. In FIG. 7C, thefocal plane is on the valleys of the wavy relief and the metalinterconnect 10 is in electrical contact with the electrode 250. Thestretchable electrode is deposited by evaporation through a shadowmaskonto a smoothly wavy elastomer substrate. In this example, the electrode250 maintains conductivity and connectivity via interconnects 10 duringstretching up to about 10% in tension.

The methods and devices disclosed herein may be used to fabricate avariety of electronic devices, including for example, a stretchablepassive matrix LED display (see FIG. 8). Wavy electrodes (e.g.,interconnects 10 and contact pad 70) are patterned on two elastomericsubstrates 30. A device component 60 (in this case ILED pixels) arepatterned on the wavy electrodes at contact pad 70 by transfer printing.The two substrates 30 are accordingly assembled such that theinterconnects 10 run in different orientations (perpendicular, in thisexample). The 2-D mechanical stretchability of such a passive matrix LEDdisplay is illustrated in FIG. 9. In addition to being able to stretchuniaxially and biaxially, the display is capable of substantial bendingwithout breaking. Such multi-axial bending provides the capability ofmolding electronic devices to curved surfaces to produce curvedelectronic devices and for incorporation into smart electronic fabricsor displays.

One such example of a curved electronic device is provided in FIG. 10.FIG. 10 illustrates an “artificial eye” comprising an inorganicphotodiode array distributed on a spherically curved lens. Fourdifferent views of the artificial array are shown. The requirement forstretchable planar electronic devices is schematically illustrated inFIG. 11. In order to wrap a planar sheet around a spherical surface, thesheet must stretch in more than one direction.

FIG. 12 is a fabrication scheme for making a stretchable buckledsemiconductor array capable of conforming to curved surfaces. Thin Sielements are fabricated with selective Au or Ti/Au deposition on asubstrate, such as the illustrated “mother wafer” in panel (i). Si isbonded to prestrained (indicated as L+ΔL) and UVO treated PDMS (panel(ii)). Prestrain is provided in two directions, as illustrated. Thebonding is by any means known in the art such as an adhesive, forexample, applied to the Si elements, the substrate, or both. The bondingmeans is applied in a selected pattern so that the Si has bonded regionsthat will remain in physical contact with the substrate (afterdeformation) and other regions in a bent configuration that are not inphysical contact with the substrate (e.g., regions that are not bondedor are weakly bonded relative to the adhesive force in the bondregions). The prestrained substrate is removed from the wafer substrateto reveal a flat grid of semiconductor arrays (panel (iii)). Uponrelaxation of the substrate from L+ΔL to L, the interconnects 10 bucklein the weakly-bonded regions (see panel (iv)) to a bent configurationwhereas the device component 60 (e.g., semiconductor Si contact pad)remains bonded to the substrate 30. Accordingly, buckled interconnects10 impart stretchability to the entire array, and specifically thecapability for motion of component 60 relative to other components 60.without breaking electrical contact between components 60, therebyproviding conformal capability to a curved surface or a bendablesurface.

FIG. 13 provides an optical microscopic image of a buckled stretchablesilicon array in a single grid configuration 140 (top two panels), gridconfiguration having a plurality of connected interconnects 160 (bottomleft panel), and a floral configuration 150 (bottom right panel). Ineach of these examples, interconnect 10 is buckled in a central portion,with interconnect ends attached to a contact pad 70. The interconnectsand contact pad 70 are supported on a PDMS substrate 30. Close-up viewsof a number of different interconnect geometries are further provided inFIGS. 14-17. FIG. 14 provides electron microscopic images to show abasic buckled or wavy interconnect 10 having a central portion 90 with afirst end 100 and second end 110. The central portion is in a bentconfiguration. Ends 100 and 110 are connected to a device component, inthis case a contact pad 70 capable of establishing electrical contactwith a device component. The interconnect 10 and contact pad 70 aresupported on a substrate 30, such as an elastomeric PDMS substrate.

FIG. 15 is an electron microscopic image of adjacent device components(e.g., contact pad 70) connected to each other by a plurality (two) ofinterconnects 160. Comparing FIG. 15 to FIG. 14 demonstrates thatadjacent device components 70 can be connected to one another by one ormore interconnects 10 to provide additional flexibility to theelectronic device. For example, a device component or contact pad 70having a relatively large footprint is optionally connected to anotherdevice component by multiple interconnects.

FIG. 16 is an electron microscopic image of interconnects in a floralconfiguration 150. A floral configuration, in contrast to a gridconfiguration, has interconnects oriented in more than two longitudinaldirections. In this example, there are four distinct orientations, sothat a device component such as contact pad 70 is capable of contactingdiagonally-adjacent device components. In this example, the interconnect10 has an optional bond region 102 in between interconnect ends 100 and110 that are electrically connected to a device component (not shown),thereby dividing central portion 90 into two non-bonded regions 92, eachhaving a bent configuration.

FIG. 17 is an electron microscopic image of interconnects arranged in abridge configuration 130. In a bridge configuration, a bridge centralportion peak 120 from which three or more interconnect ends extendtherefrom. For example, two interconnects that intersect in a non-bondedregion results in a peak 120 having four interconnect ends extendingtherefrom. For the situation where the device components are in astaggered arrangement, the peak 120 may have three ends extendingtherefrom. In the case of multiple interconnect connections betweendevice components, more than four ends may extend from peak 120.

Although many of the drawings provided herein show a device componentthat is a contact pad 70, the methods and devices claimed herein arecapable of connecting to a vast population of device components toprovide stretchable and therefore shape-conforming, electronic devices.For example, FIG. 18 shows a device component 60 that is a photodiodeconnected to other photodiodes in an array configuration by buckledinterconnects 10 supported on an elastomeric substrate 30.

FIG. 19 depicts one-dimensional stretching behavior of a buckled siliconarray. Panel (i) is a picture of a buckled silicon array without anystraining force applied. A stretching force is applied (as indicated bythe arrows above panel (i)) to stretch the array in one direction. Asshown in panels (2)-(4), the buckled interconnect flattens. When thestretching force is released in panel (5), the array reverses to itsbuckled configuration (see panels (6)-(8)). A comparison between panels(1) and (8) shows that the buckle configuration pre and post-stretch areidentical, indicating the process is reversible.

Buckled arrays of device components may be readily transferred to curvedsurfaces, including rigid or inelastic curved surfaces. An example ofone device and process for facilitating conformal contact to curvedsurfaces is provided by the bubble or balloon stamp 400 of FIG. 20. Anelastomeric substrate 30, in this example an about 20 μm thick PDMSmembrane is fixed in a housing chamber 300 to provide a chamber volume310 defined by the interior-facing substrate wall and housing chamber.Applying a positive pressure (e.g., pressure in chamber 300 greater thanexterior pressure) generates a convex 200 substrate surface capable ofconformal contact with a concave-shaped receiving substrate. A negativepressure, in contrast, generates a concave surface 210 capable ofconformal contact with a convex-shaped receiving substrate. Spatialmanipulation of local elasticity (e.g., Young's modulus) of thesubstrate permits generation of complex curved geometry. The bottom leftpanel of FIG. 20 illustrates one means for controlling the pressure inthe housing volume 310 by a syringe that introduces or removes gas toand from chamber 310. The images on the right side of the figure aredifferent curvatures of a PDMS membrane in response to increasing levelof positive pressure. Any of the methods and devices for providingbuckled interconnects on an elastomeric substrate may be used with suchdevices for transfer printing to a curved substrate.

Another means for generating buckled or pop-up interconnects on a curvedsurface is summarized in FIG. 21. A thin elastomeric film is castagainst a shaped surface to generate an elastomeric substrate having atleast a portion that is curved. The substrate is capable of beingstretched to flatten the surface so that the substrate is capable ofconforming to both curved and flat surfaces. An interconnect is appliedto the flat stamp, and upon release of the stretching force, thesubstrate surface relaxes back to a curved geometry, generating a strainin the interconnect that is accommodated by a pop-up of the interconnectcentral portion.

An example of “two-dimensional” stretching of a buckled silicon array bythe device shown in FIG. 20, is provided in FIG. 22. In this example,the interconnect comprises a plurality of buckled interconnectconnections in a grid configuration, with the interconnects made of 290nm thick Si. The initially flat buckled silicon array (top left image)is placed into the housing, and a positive pressure exerted to expandthe array into a bubble or balloon configuration (e.g., a curvedsurface). Maximum expansion is shown in the right-most image, andsubsequently the positive pressure removed. Similar to the results foruniaxial stretching of a flat substrate, this “bending” stretching isreversible. At any stage of expansion, that maximizes conformal contactwith a curved surface, the array may be transferred to the curvedsurface by any means known in the art. An example of silicon printing byballoon stamps onto glass lenses coated with adhesives (elastomericsubstrate or SU-8) is shown in FIG. 23. The lens may be either concaveor convex. In this example R=19.62 mm and 9.33 mm, respectively.

Example 1 Controlled Buckling Structures in Semiconductor Nanoribbonswith Application Examples in Stretchable Electronics

Control over the compositions, shapes, spatial locations and/orgeometrical configurations of semiconductor nanostructures is importantfor nearly all applications of these materials. Although methods existfor defining the material compositions, diameters, lengths, andpositions of nanowires and nanoribbons, there are relatively fewapproaches for controlling their two- and three-dimensional (2D and 3D)configurations. Provided herein is a mechanical strategy for creatingcertain classes of 3D shapes in nanoribbons that are otherwise difficultto generate. This example involves the combined use of lithographicallypatterned surface chemistry to provide spatial control over adhesionsites and elastic deformations of a supporting substrate to inducewell-controlled local displacements. Precisely engineered bucklinggeometries are created in nanoribbons of GaAs and Si in this manner andthese configurations can be described quantitatively with analyticalmodels of the mechanics. As one applications example, particularstructures provide a route to electronics (and optoelectronics) withextremely high levels of stretchability (up to ˜100%), compressibility(up to ˜25%) and bendability (with curvature radius down to ˜5 mm).

The 2D and 3D configurations of nanoribbons and wires are controlledduring their growth to yield certain geometries, such as coils, rings,and branched layouts, or after their growth to produce, as examples,sinusoidal wave-like structures by coupling these elements to strainedelastomeric supports or tube-like (or helical) structures by usingbuilt-in residual stresses in layered systems. Semiconductor nanoribbonswith wavy geometries are of interest in part because they enable highperformance, stretchable electronic systems for potential applicationssuch as spherically curved focal plane arrays, intelligent rubbersurgical gloves and conformable structural health monitors. Thisapproach, in which the electronic devices themselves are stretchable, isdifferent than and perhaps complementary to an alternative route tothese same applications that use rigid device islands with stretchablemetal interconnects. The previously described wavy nanoribbons have twomain disadvantages: (i) they form spontaneously, with fixed periods andamplitudes defined by the moduli of the materials and the thicknesses ofthe ribbons, in a way that offers little control over the geometries orthe phases of the waves and (ii) the maximum strains that they canaccommodate are in the range of 20-30%, limited by the non-optimal wavygeometries that result from this process. The procedures introduced hereuse lithographically defined surface adhesion sites together withelastic deformations of a supporting substrate to achieve bucklingconfigurations with deterministic control over their geometries.Periodic or aperiodic designs are possible, for any selected set ofindividual nanoribbons in large scale, organized arrays of suchstructures. Specialized geometries designed for stretchable electronicsenable strain ranges of up to nearly 150%, even in brittle materialssuch as GaAs, consistent with analytical modeling of the mechanics, andas much as ten times larger than previously reported results.

FIG. 24 shows the steps in this procedure. The fabrication starts withthe preparation of a mask for patterning surface chemical adhesion siteson an elastomeric substrate of poly(dimethylsiloxane) (PDMS). Thisprocess involves passing deep ultraviolet (UV) light (240-260 nm)through an unusual type of amplitude photomask (fabricated via step i),referred to as a UVO mask, while it is in conformal contact with thePDMS. The UVO mask possesses recessed features of relief in thetransparent regions, such that exposure to UV creates patterned areas ofozone in proximity to the surface of the PDMS. The ozone converts theunmodified hydrophobic surface, dominated by —CH₃ and —H terminalgroups, to a highly polar and reactive surface (i.e. activated surface),terminated with —OH and —O—Si—O— functionalities. The unexposed areasretain the unmodified surface chemistry (i.e. inactivated surface). Theprocedures introduced here involve exposures on PDMS substrates(thickness ˜4 mm) under large, uniaxial prestrains (∈_(p)=ΔL/L forlengths changed from L to L+ΔL) (step ii). For masks with simple,periodic line patterns, we denote the widths of the activated (indicatedas lines labeled “activated surface”) in step (iii) of FIG. 24A andinactivated stripes (e.g., the distance between adjacent activatedstripes) as W_(act) and W_(in) in step (i). The activated areas can bondstrongly and irreversibly to other materials that have exposed —OH or—Si—O groups on their surfaces. These patterned adhesion sites areexploited to create well defined 3D geometries in nanoribbons, asoutlined below. Alternatively, a similar adhesive bond site pattern isprovided by similarly patterning the interconnects prior to contact withthe substrate.

In this example, nanoribbons consisted of both single crystal Si andGaAs. The silicon ribbons are prepared from silicon-on-insulator (SOI)wafers using procedures described previously (see Khang et al. Science311, 208-212 (2006)). The GaAs ribbons involved multilayers of Si-dopedn-type GaAs (120 nm; carrier concentration of 4×10¹⁷ cm³),semi-insulating GaAs (SI—GaAs; 150 nm) and AlAs (200 nm) formed on a(100) SI—GaAs wafer by molecular-beam epitaxy (MBE). Chemically etchingthe epilayers in an aqueous etchant of H₃PO₄ and H₂O₂, using lines ofphotoresist patterned along the (0 1 1) crystalline orientation as etchmasks, define the ribbons. Removing the photoresist and then soaking thewafer in an ethanol solution of HF (2:1 in volume between ethanol and49% aqueous HF) removes the AlAs layer, thereby releasing ribbons ofGaAs (n-GaAs/SI—GaAs) with widths determined by the photoresist (˜100 μmfor the examples in FIG. 24D). The addition of ethanol to the HFsolution reduces the probability of cracking of the fragile ribbons dueto the action of capillary forces during drying. The low surface tension(compared to water) also minimizes drying-induced disorder in thespatial layout of the GaAs ribbons. In the final step, a thin layer ofSiO₂ (˜30 nm) is deposited to provide the necessary —Si—OH surfacechemistry for bonding to the activated regions of the PDMS.

Laminating the processed SOI or GaAs wafers against a UVO treated,pre-stretched PDMS substrate (ribbons oriented parallel to the directionof prestrain), baking in an oven at 90° C. for minutes, and removing thewafer transferred all of the ribbons to the surface of the PDMS (stepiv). Heating facilitates conformal contact and the formation of strongsiloxane bonds (i.e., —O—Si—O—) between the native SiO₂ layer on the Siribbons or the deposited SiO₂ layer on the GaAs ribbons and theactivated areas of the PDMS. Relatively weak van der Waals forces bondthe ribbons to the inactivated surface regions of the PDMS. Relaxing thestrain in the PDMS generates buckles through the physical separation ofthe ribbons from the inactivated regions of the PDMS (step v). Theribbons remain tethered to the PDMS in the activated regions due to thestrong chemical bonding. The resulting 3D ribbon geometries (i.e. thespatially varying pattern of buckles) depend on the magnitude ofprestrain and the patterns of surface activation (e.g., shape anddimensions of W_(in) and W_(act)). (Similar results can be achievedthrough patterned bonding sites on the ribbons). For the case of thesimple line pattern, W_(in) and the prestrain determine the width andamplitude of the buckles. Sinusoidal waves with wavelengths andamplitudes much smaller than the buckles also formed in the same ribbonswhen W_(act) was >100 μm, due to mechanical instabilities of the typethat generate ‘wavy’ silicon. (see FIG. 25, images of samples formedwith different W_(act)). As a final step in the fabrication, the 3Dribbon structures can be encapsulated in PDMS by casting and curing aliquid prepolymer (see FIG. 24 step vi). Due to its low viscosity andlow surface energy, the liquid flows and fills the gaps formed betweenthe ribbons and the substrate (see FIG. 26).

FIG. 24D shows a tilted-view scanning electron microscope (SEM) image ofbuckled GaAs ribbons on PDMS, in which ∈_(pre)=60% and with W_(act)=10μm and W_(in)=400 μm. The image reveals uniform, periodic buckles withcommon geometries and spatially coherent phases for all ribbons in thearray. The anchoring points are well registered to the lithographicallydefined adhesion sites. The inset shows an SEM image of a bonded region;the width is ˜10 μm, consistent with W_(act). The images also revealthat the surface of the PDMS is flat, even at the bonding sites. Thisbehavior, which is much different than the strongly coupled wavystructures reported previously, suggests that the PDMS induces thedisplacements but is not intimately involved in the buckling process(i.e. its modulus does not affect the geometries of the ribbons), forthe cases described here. In this sense, the PDMS represents a soft,nondestructive tool for manipulating the ribbons through forces appliedat the adhesion sites.

FIG. 27A shows side-view optical micrographs of buckled ribbons formedon PDMS with different ∈_(pre) (W_(act)=10 μm and W_(in)=190 μm). Theheights of the buckles (e.g., “amplitude”) increase with ∈_(pre). Theribbons in the inactivated regions do not fully separate at low ∈_(pre)(see the samples formed with ∈_(pre)=11.3% and 25.5%). At higher∈_(pre), the ribbons (thickness h) separate from the PDMS to formbuckles with vertical displacement profiles characterized by:

$y = {\frac{1}{2}{A_{1}^{0}\left\lbrack {1 + {\cos \left( {\frac{\pi}{L_{1}}x} \right)}} \right\rbrack}}$

Where:

$A_{1}^{0} = {\frac{4}{\pi}\sqrt{L_{1}{L_{2}\left( {ɛ_{pre} - \frac{h^{2}\pi^{2}}{12L_{1}^{2}}} \right)}}}$$L_{1} = \frac{W_{in}}{2*\left( {1 + ɛ_{pre}} \right)}$$L_{2} = {L_{1} + \frac{W_{act}}{2}}$

as determined by nonlinear analysis of buckles formed in a uniform, thinlayer. The maximum tensile strain in the ribbons is, approximately,

$ɛ_{peak} = {\kappa {_{\max}{\frac{h}{2} = {y^{n}{_{\max}{\frac{h}{2} = {\frac{h}{4}{A_{1}^{0}\left( \frac{\pi}{L_{1}} \right)}^{2}}}}}}}}$

The width of the buckles is 2L₁ and the periodicity is 2L₂. Becauseh²π²/(12L₁ ²) is much smaller than ∈_(pre) (i.e., >10% in the report)for h<1 μm, the amplitude is independent of the mechanical properties ofribbons (e.g., thickness, chemical composition, Young's modulus, etc.)and is mainly determined by the layout of adhesion sites and theprestrain. This conclusion suggests a general applicability of thisapproach: ribbons made of any material will form into similar buckledgeometries. This prediction is consistent with the results obtained withSi and GaAs ribbons used here. The calculated profiles, plotted asdotted lines in FIG. 27A for pre-strains of 33.7% and 56.0%, agree wellwith the observations in GaAs ribbons. Further, the parameters(including periodicity, width, and amplitude) of the buckles shown inFIG. 27A are consistent with analytical calculations, except at low∈_(pre) (Tables 1 and 2). An interesting result of this study is thatthe maximum tensile strains in the ribbons are small (e.g. ˜1.2%), evenfor large ∈_(pre) (e.g. 56.0%). This scaling enables stretchability,even with brittle materials such as GaAs, as discussed subsequently.

The lithographically defined adhesion sites can have more complexgeometries than the simple grating or grid patterns associated with thestructures in FIG. 24. For example, buckles with different widths andamplitudes can be formed in individual ribbons. FIG. 27B shows, as anexample, an SEM image of buckled Si ribbon (widths and thicknesses of 50μm and 290 nm, respectively), formed with a prestrain of 50% andadhesion sites characterized by W_(act)=15 μm and W_(in)=350, 300, 250,250, 300, and 350 μm along the lengths of the ribbons. The image clearlyshows the variation of widths and amplitudes of adjacent buckles in eachof the ribbons. Buckled ribbons can also be formed with different phasesfor different ribbons. FIG. 27C presents an example of a Si systemdesigned with phases in the buckles that vary linearly with distanceperpendicular to the lengths of the ribbons. The UVO mask used for thissample has W_(act) and W_(in) of 15 and 250 μm, respectively. The anglebetween the activated stripes on PDMS stamp and Si ribbons is 30°. Manyother possibilities can easily be achieved, due to the simplelithographic control of the adhesion sites, and some are shown in FIGS.13-17, for example.

The simple case of buckled GaAs ribbons on PDMS with ∈_(pre)=60%,W_(act)=10 μm and different W_(in), as shown in FIG. 27D, illustrates anaspect that is important for applications in stretchable electronics.The profiles, which agree well with analytical solutions to themechanics, show failure due to cracking in the GaAs when W_(in)=100 μm(and smaller). The failure results from tensile strains (˜2.5% in thiscase) that exceed the yield point of the GaAs (˜2%). An optimizedconfiguration for robustness to stretching and compressing can,therefore, be achieved by selecting W_(in) (>>W_(act)) proportional to∈_(pre). In this situation, prestrains up to and greater than 100% canbe accommodated. We demonstrated this type of stretchability directly byapplying forces to the PDMS supports. Changes in the end-to-enddistances (L_(projected)) of segments of the ribbons provided a means toquantify the stretchability and compressibility, according to:

${{\frac{L_{projected}^{\max} - L_{projected}^{0}}{L_{projected}^{0}}}*100\%},$

Where L_(projected) ^(max) represents the maximum/minimum length beforefracture and L_(projected) ⁰ is the length in the relaxed state.Stretching and compressing correspond to L_(projected) ^(max) greaterand less than L_(projected) ⁰, respectively. Buckled ribbons on PDMSwith W_(act)=10 μm and Win=400 μm and ∈_(pre)=60%, exhibitstretchability of 60% (i.e., ∈_(pre) and compressibility up to 30%.Embedding the ribbons in PDMS mechanically protects the structures, andalso produces a continuous, reversible response, but with slight changesin the mechanics. In particular, the stretchability and compressibilitydecreased to ˜51.4% (FIG. 28A) and ˜18.7% (FIG. 28B), respectively. ThePDMS matrix on top of the ribbons flattens the peaks of the bucklesslightly, due partly to curing induced shrinkage of the overlying PDMS.Small period waves form in these regions under large compressivestrains, due to the spontaneous mechanics of the type that generated thewavy ribbon structures described previously. Mechanical failure tendedto initiate in these areas, as illustrated in FIG. 28B, thereby reducingthe compressibility. Buckled structures with W_(act)=10 μm andW_(in)=300 μm avoided this type of behavior. Although such samplesexhibited slightly lower stretchability than the one shown in FIG. 28A,the absence of the short period waves increased the compressibility to˜26%. Overall, single-crystalline GaAs nanoribbons with buckles formedon the pre-stretched PDMS substrates with patterned surface chemicaladhesion sites exhibit stretchability higher than 50% andcompressibility larger than 25%, corresponding to full scale strainranges approaching 100%. These numbers are further improved byincreasing ∈_(pre) and W_(in) and by using a substrate material capableof higher elongation than PDMS. For even more elaborate systems, thesefabrication procedures can be repeated to generate samples with multiplelayers of buckled ribbons (see FIG. 29).

A direct consequence of this large stretchability/compressibility isextreme levels of mechanical bendability. FIG. 30A-C present opticalmicrographs of bent configurations that illustrate this feature. ThePDMS substrate (thickness ˜4 mm) is bent into concave (radius of ˜5.7mm), flat, and convex (radius of ˜6.1 mm) curvatures, respectively. Theimages illustrate how the profiles changed to accommodate the bendinginduced surface strains (˜20-25% for these cases). The shapes aresimilar, in fact, to those obtained in compression (by ˜20%) and tension(by ˜20%). The embedded systems exhibit even higher levels ofbendability due to neutral mechanical plane effects. When the top andbottom layers of PDMS had similar thicknesses, there was no change inthe buckling shapes during bending (FIG. 30D).

To demonstrate these mechanical properties in functional electronicdevices, we build metal semiconductor-metal photodetectors (MSM PDs)using buckled GaAs ribbons with profiles similar to those shown in FIG.30, by depositing thin gold electrodes onto the SI—GaAs sides of theribbons for Schottky contacts. FIG. 31A shows the geometry andequivalent circuit, and top-view optical micrographs of an MSM PD beforeand after stretching by ˜50%. In the absence of light, little currentflowed through the PD; the current increased with increasingillumination with an infrared beam (wavelength ˜850 nm) (FIG. 31B). Theasymmetry in the current/voltage (I-V) characteristics can be attributedto differences in the electrical properties of the contacts. FIG. 31C(stretching) and FIG. 31D (compressing) show I-Vs measured at differentdegrees of stretching and compressing. The current increased when the PDwas stretched by up to 44.4% and then decreased with further stretching.Because the intensity per unit area of the light source is constant, theincreases in current with stretching can be attributed to increases inthe projected area (referred to as effective area, S_(eff)) of thebuckled GaAs ribbon as it flattens. Further stretching the PD mightinduce the formation of defects on the surface and/or in the lattice ofthe GaAs ribbon, resulting in the decrease of current and eventually, atfracture, an open circuit. Similarly, compression decreased S_(eff) andthus decreased the current (FIG. 31D). These results indicate thatbuckled GaAs ribbons embedded in PDMS matrix provide a fullystretchable/compressible type of photosensor useful for variousapplications, such as wearable monitors, curved imaging arrays and otherdevices.

In conclusion, this example indicates that soft elastomers withlithographically defined adhesion sites are useful as tools for creatingcertain classes of 3D configurations in semiconductor nanoribbons.Stretchable electronics provide one example of the many possibleapplication areas for these types of structures. Simple PD devicesdemonstrate some capabilities. The high level of control over thestructures and the ability to separate high temperature processing steps(e.g. formation of ohmic contacts) from the buckling process and thePDMS indicate that more complex devices (e.g. transistors, and smallcircuit sheets) are possible. The well controlled phases of buckles inadjacent ribbons provide an opportunity for electrically interconnectingmultiple elements. Also, although the experiments reported here usedGaAs and Si nanoribbons, other materials (e.g. GaN, InP, and othersemiconductors) and other structures (e.g. nanowires, nanomembranes) arecompatible with this approach.

Fabrication OF GaAs Ribbons:

GaAs wafers with customer-designed epitaxial layers (details describedin the text) were purchased from IQE Inc., Bethlehem, Pa.Photolithography and wet chemical etching generated the GaAs ribbons. AZphotoresist (e.g., AZ 5214) was spin cast on the GaAs wafers at speed of5000 rpm for 30 seconds and then soft baked at 100° C. for 1 minute.Exposure through a photomask with patterned lines oriented along the (01 1) crystallographic direction of GaAs, followed by developmentgenerated line patterns in the photoresist. Mild O₂ plasma (i.e., descumprocess) removed the residual photoresist. The GaAs wafers were thenanisotropically etched for 1 minute in the etchant (4 mL H₃PO₄ (85 wt%), 52 mL H₂O₂ (30 wt %), and 48 mL deionized water), cooled in theice-water bath. The AlAs layers were dissolved with an HF solution(Fisher® Chemicals) diluted in ethanol (1:2 in volume). The samples withreleased ribbons on mother wafers were dried in a fume hood. The driedsamples were coated with 30 nm SiO₂ deposited by electron beamevaporation.

Fabrication of Si Ribbons:

The silicon ribbons are fabricated from an silicon-on-insulator (SOI)wafer (Soitect, Inc., top silicon 290 nm, buried oxide 400 nm, p-type).The wafer is patterned by conventional photolithography using AZ 5214photoresist and etched with SF6 plasma (PlasmaTherm RIE, SF6 40 sccm, 50mTorr, 100 W). After the photoresist is washed away with acetone, theburied oxide layer is then etched in HF (49%).

Fabrication of UVO Masks:

Fused quartz slides are cleaned in piranha solution (at 60° C.) for 15minutes and thoroughly rinsed with plenty of water. The cleaned slidesare dried with nitrogen blowing and placed in the chamber ofelectron-beam evaporator to be coated with sequential layers of 5-nm Ti(as adhesive layer) and 100-nm Au (mask layer for UV light). Negativephotoresist, i.e., SU8 5, is spin cast on the slides at speed of 3000rpm for 30 seconds to yield ˜5 μm thick films. Soft baking, exposing toUV light, post baking, and developing generated patterns in thephotoresist. Mild O₂ plasma (i.e., descum process) removes the residualphotoresist. The photoresist serves as mask to etch Au and Ti using goldetchant (i.e., aqueous solution of I2 and KI) and titanium etchant(i.e., diluted solution of HCl), respectively.

Preparation of PDMS Stamps:

PDMS substrates with thickness of ˜4 mm were prepared by pouring theprepolymer (A:B=1:10, Sylgard 184, Dow Corning) into a Petri dish,followed by baking at 65° C. for 4 hours. Slabs with suitable sizes andrectangular shapes were cut from the resulting cured piece and therinsed with isopropyl alcohol and dried with nitrogen blowing. Aspecially designed stage was used to mechanically stretch the PDMS todesired levels of strain. Illuminating these stretched substrates toshort-wavelength UV light (low-pressure mercury lamp, BHK, 173 μW/cm2from 240 to 260 nm) for 5 min through a UVO mask placed in contact withthe PDMS generated the patterned surface chemistries.

Formation and Embedment of Buckled GaAs Ribbons:

GaAs wafers with released ribbons coated with SiO₂ were laminatedagainst the stretched PDMS with patterned surface chemistry. Baking inan oven at 90° C. for 5 minutes, cooling to room temperature in air, andthen slowly relaxing the strain in the PDMS generated buckles along eachribbon. Embedding the buckled ribbons, involved flood exposing to UVlight for 5 minutes and then casting of liquid PDMS prepolymers to athickness of ˜4 mm. Curing the sample either in an oven at 65° C. for 4hours or at room temperature for 36 hours cured the prepolymer, to leavethe buckled ribbons embedded in a solid matrix of PDMS.

Characterization of Buckled Ribbons:

The ribbons were imaged with an optical microscope by tilting the sampleby ˜90° (for nonembedded samples) or ˜30° (for embedded samples). TheSEM images were recorded on a Philips XL30 field-emission scanningelectron microscope after the sample was coated with a thin layer ofgold (˜5 nm in thickness). The same stage used for pre-stretching thePDMS stamps was used to stretch and compress the resulting samples.

Fabrication And Characterization of SMS PDs:

Fabrication of PDs started with samples in the configuration shown inthe bottom frame of FIG. 24B. A ˜0.8 mm wide strip of poly(ethyleneterephthalate) (PET) sheet was gently placed on the PDMS with itslongitudinal axis perpendicular to the longitudinal axes of the ribbons.This strip served as a shadow mask for electron beam evaporation of a30-nm thick gold film (to form Schottky electrodes). Removing the PETstripe, and relaxing the pre-stretched PDMS stamp formed SMS PDs builtwith buckled GaAs ribbons. Liquid PDMS prepolymer was cast onto theregions of the ribbons without electrodes and then cured in an oven. Thegold electrodes extended beyond the top PDMS to enable probing with asemiconductor parameter analyzer. (Agilent 4155C). In measurements ofthe photoresponse, the PDs were manipulated using a mechanical stage forstretching and compressing. An IR LED source (with wavelength of 850 nm)provided the illumination.

Example 2 Transfer Printing

Our technical approach uses certain ideas embodied in the planar stampbased printing methods previously described. Although these basictechniques provide a promising starting point, many fundamentally newfeatures must be introduced to meet the challenges of the HARDI(Hemispherical Array Detector for Imaging) system, as described in thefollowing.

FIGS. 32 and 33 illustrate a general strategy related to transferprinting to curved surfaces. The first set of steps (FIG. 32) involvesthe fabrication and manipulation of a thin, spherically curvedelastomeric stamp designed to lift off interconnected Si CMOS ‘chiplets’from the planar surface of a wafer and then to transform the geometryinto a hemispherical shape. A stamp for this process is formed bycasting and curing a liquid prepolymer to obtain an elastomer such aspoly(dimethylsiloxane) (PMDS) against high quality optical elements(i.e. a matched pair of convex and concave lenses) selected with therequired radii of curvature. The stamp has a molded circular rim.Radially stretching this element by mating the molded groove (dashedcircle in FIG. 32) on this rim onto an appropriately sized rigid,circular retaining ring transforms this spherical stamp into astretched, planar sheet. Contacting this stretched stamp to a motherwafer that supports preformed and undercut etched Si CMOS ‘chiplets’with thin interconnects and then peeling the stamp away ‘inks’ thiselement with these interconnected ‘chiplets’. Van der Waals interactionsbetween the chiplets and the soft, elastomeric element providessufficient adhesion for this process.

Removing the retaining ring causes the PDMS to relax back to its initialhemispherical shape, thereby accomplishing a planar to sphericaltransformation of the chiplet array. This transformation inducescompressive strains at the surface of the stamp. These strains areaccommodated in the CMOS chiplet array by local delamination and liftingup of the interconnects (bottom left of FIG. 32). These ‘pop-up’interconnects absorb the strains in a manner that avoids damage to thechiplets or detrimental strain-induced changes in their electricalproperties. Maintaining the strains in the chiplets below ˜0.1%accomplishes these two goals. The space required for the interconnectslimits the maximum fill factor of the CMOS chiplets. Thephotodectectors, however, consumes nearly the full pixel areas, therebyproviding a straightforward path to an 80% fill factor target.

In the second set of steps (FIG. 33), the ‘inked’ hemispherical stamp isused to transfer print these elements onto the final device substratehaving a matching shaped cavity (e.g., in this example a glass substratewith a matching hemispherically-shaped cavity). This transfer processuses an ultraviolet (UV) curable photopolymer, such as photocurable BCB(Dow Chemical) or polyurethane (Norland Optical Adhesive) as anadhesive. These materials are applied to the device substrate in theform of a thin (tens of microns thick) liquid film. Upon contact withthe stamp, this liquid layer flows to conform to the relief structuresassociated with the chiplets and the pop-up interconnects. UV lightpassed through the transparent substrate cures the photopolymer andtransforms it into a solid form to yield a smooth, planarized topsurface upon removal of the stamp. Final integration to form afunctional system involves the deposition and patterning of electrodesand photodetector materials, and lithographic definition of the buslines to external control circuits.

The approach of FIGS. 32 and 33 has several notable features. First, itexploits state-of-the-art planar electronics technology to enablereliable, cost-effective and high performance operation on thehemispherical substrates. In particular, the chiplets consist ofcollections of silicon transistors processed at the 0.13 μm design ruleto yield the local, pixel-level processing capabilities for the HARDIsystem. Conventional processing is used with silicon-on-insulator wafersto form these devices.

The buried oxide provides the sacrificial layer (undercut etching withHF) to prepare the chiplets for printing. The interconnects consist ofnarrow and thin (˜100 nm) metal lines.

A second feature is that the approach uses elastomeric elements andmechanical designs to enable a well-controlled planar to hemisphericaltransformation. Reversible, linear mechanics in the transfer stamps andcomprehensive mechanical modeling accomplishes this control, as outlinedsubsequently. A third attractive aspect is that certain basic componentsof the transfer processes and strategies to control adhesion have beendemonstrated in planar applications. In fact, the stages that have beenengineered for those planar printing applications can be adapted for theprocess of FIGS. 32 and 33. FIG. 34 shows a home-built printer withintegrated vision systems and air pressure actuators suitable for use inthis process.

These types of printer systems are used to demonstrate several aspectsof the process of FIGS. 32 and 33. FIG. 35 shows scanning electronmicrograph images of the surface of a hemispherical stamp that is‘inked’ with an array of single crystal silicon islands interconnectedin a square array with heavily doped silicon ribbons. FIG. 36 showsoptical images. During the planar to spherical transformation, theseribbon interconnects pop up in the manner depicted in FIG. 32. A keyaspect of these types of interconnects is that, when combined with thetransfer of fully formed chiplets, they reduce the need for highresolution, curved surface lithography or other forms of processingdirectly on the hemisphere.

In addition to materials and general processing strategies, fullcomputational modeling of the elastic mechanical response of thehemispherical stamps, the pop-up interconnects and the interactions withthe rigid device islands is performed. These calculations reveal thephysics of the process at a level that facilitates engineering controland optimization. Simple estimates based on linear elastic plate theorysuggest that the strain levels associated with the processes of FIG. 32can reach 10% or higher for a 2 mm-thick stamp and a sphere with 1 cmradius. For reliable engineering control, it is necessary, therefore,that the stamp is operated in the linear elastic regime for strains upto twice this value—i.e. ˜20%. FIG. 37 shows experimental stress/straincurves of several variants of PDMS with which we have experience at thelevel of bulk, planar stamp based printing. The 184-PDMS appears toprovide a good initial material because it provides highly linear andelastic response up to strains of ˜40%.

Mechanical measurements such as these, coupled with literature valuesfor the moduli and geometries of the chiplets and the ribbon pop-upinterconnects, provide information necessary for the modeling. Twoapproaches to the calculations are adopted. The first is full-scalefinite element modeling (FEM), in which the details of device andinterconnect geometry (e.g., size, spacing, multi-layers) on the planarsubstrate are analyzed. Different materials (e.g., stamp, silicon,interconnects) are accounted for directly in the analysis. A lateralpressure is imposed to deform the stamp and circuits onto the desiredspherical shape. The finite element analysis gives the straindistribution, particularly the maximum strain in devices andinterconnects, and non-uniform spacing between transformed devices. Theadvantage of such an approach is that it captures all the details ofdevice geometry and materials, and therefore can be used to explore theeffects of different designs of transfer printing process in order toreduce the maximum strain and non-uniformity. This approach, however, iscomputationally intensive and therefore, time consuming since itinvolves a wide range of length scales, and the modeling of largenumbers of structures devices on the stamp.

The second approach is a unit-cell model for devices (chiplets) thatanalyzes their mechanical performance upon loading. Each device isrepresented by a unit cell, and its response upon mechanical loading(e.g., bending and tension) is studied thoroughly via the finite elementmethod. Each device is then replaced by the unit cell linked byinterconnects. This unit-cell model is then incorporated into the finiteelement analysis to replace the detailed modeling of devices andinterconnects. Furthermore, away from the edge of the sphere, thestrains are relatively uniform such that the many unit-cells can beintegrated and their performance can be represented by a coarse-levelmodel. Near the sphere edge the strains are highly non-uniform such thatthe detailed modeling of devices are still necessary. The advantage ofsuch an approach is that it significantly reduces the computationaleffort. The full-scale finite element analysis in the first approach isused to validate this unit-cell model. Once validated, the unit-cellmodel provides a powerful design tool since it is suitable for the quickexploration of different designs of devices, interconnects, and theirspacing.

FIG. 38 presents preliminary FEM results for stretching a hemisphericalstamp into a planar geometry (and relaxing it back to its hemisphericalshape), as outlined in FIG. 32. The top frame shows a cross sectionalview of a hemispherical stamp with a geometry like the one schematicallyillustrated in FIG. 32. These results show slight spatialnon-uniformities in the strains of the stretched membrane, as evidencedby its non-uniform thickness. Engineering the thickness profiles of thestamps, through proper selection of the structures against which theyare formed by casting and curing, can eliminate these non-uniformities.It is important to note, however, that some non-uniform strains areacceptable because (i) the pop-up interconnects are inherentlydistortion tolerant, and (ii) the chiplets do not have to be centeredperfectly at each pixel location; the larger photodetectors will fillthe pixel areas with a uniform back electrode that can establishelectrical contact to the chiplets independent of their positions withinthe pixel areas.

The modeling can also determine the levels of strain in the Si CMOSchiplets. The systems should be designed to keep these chiplet strainsbelow ˜0.1-0.2% to avoid changes in the electrical properties and,possibly, mechanical failures due to fracture or delamination. Thismodeling facilitates the design of stamps and processing conditions toavoid exposure of the chiplets to strains above this range.

Example 3 Biaxially Stretchable “Wavy” Silicon Nanomembranes

This example introduces a biaxially stretchable form of singlecrystalline silicon that consists of two dimensionally buckled, or“wavy”, silicon nanomembranes on elastomeric supports. Fabricationprocedures for these structures are described, and various aspects oftheir geometries and responses to uniaxial and biaxial strains alongvarious directions are presented. Analytical models of the mechanics ofthese systems provide a framework for quantitatively understanding theirbehavior. These classes of materials provides a route tohigh-performance electronics with full, two-dimensional stretchability.

Electronics that offer mechanically bendability are of interest forapplications in information display, X-ray imaging, photovoltaicdevices, and other systems. Reversible stretchability is a different andmuch more technically challenging mechanical characteristic that wouldenable device possibilities that cannot be realized with electronicsthat are only bendable, such as smart surgical gloves, electronic eyecameras, and personal health monitors. In one approach to electronics ofthis type, stretchable wires interconnect rigid device islands toprovide circuit level stretchability with device components that are notstretchable. In an alternative strategy, certain structural forms ofthin single-crystal semiconductor and other electronic materials allowstretchability in the devices themselves. Recent demonstrations involvedthe use of buckled, one-dimensional “wavy” geometries in nanoribbons(thicknesses between tens and hundreds of nanometers and widths in themicrometer range) of silicon and gallium arsenide to achieve uniaxialstretchability in metal oxide semiconductor field effect transistors(MOSFETs), metal semiconductor field effect transistors (MESFETs), pnjunction diodes, and Schottky diodes. This example shows thatnanomembranes of similar materials can be formed into two-dimensional(2D) wavy geometries to provide full 2D stretchability. The fabricationprocedures for such systems are described, together with detailedexperimental characterization and analytical modeling of theirmechanical response.

FIG. 39 schematically illustrates the steps for formingtwo-dimensionally stretchable Si nanomembranes on elastomeric supports.For this example, these membranes are fabricated fromsilicon-on-insulator (SOI) wafers (Soitec, Inc., p-type) starting withthe formation of a square array of holes in the top silicon (˜2.5 μmdiameter, and ˜25 μm pitch), by defining suitable patterns ofphotoresist by photolithography and then removing the exposed silicon byreactive ion etching (PlasmaTherm RIE, SF₆ 40 sccm, 50 mTorr, 100 W).This same step defines the overall lateral dimensions of the membraneswhich, for the samples reported here, are in the range of 3-5 mm square.The thicknesses are between 55 and 320 nm. Immersing the etched samplesin concentrated hydrofluoric acid (HF 49%) removes the buried SiO₂ layer(145˜1000 nm thick); washing in acetone removed the photoresist. Castingand curing prepolymers of poly(dimethylsiloxane) (PDMS) against polishedsilicon wafers generated flat, elastomeric substrates (˜4 mm thick).Exposure to an ozone environment created by intense ultraviolet light(240-260 nm) for 5 min converted the hydrophobic PDMS surface (—CH₃ and—H end groups) to a hydrophilic state (—OH and —O—Si—O end groups).Heating such an activated PDMS substrate briefly at 70-180° C. in aconvection oven induced a controlled degree of isotropic thermalexpansion. Contacting this element to the processed SOI wafer and thenpeeling it off again transferred the entire nanomembrane to the PDMS.Continued heating in the convection oven for a few minutes facilitatedthe formation of strong adhesive bonds between the membrane and thePDMS. In the final step, the nanomembrane/PDMS structure i cooled toroom temperature (ca. 25° C.) to release the thermally induced prestrain(ΔL/L). This process led to the spontaneous formation of two-dimensional(2D) wavy structures of relief in the Si nanomembrane and the nearsurface region of the PDMS. These structures exhibit different behaviorsnear the edges, where one-dimensional periodic waves predominate, at theinner regions, where two-dimensional herringbone layouts are typicallyobserved, and near the centers, where disordered herringbone structuresoften occur. The herringbone region is characterized by the distancebetween adjacent peaks in the waves, which we refer to as the shortwavelength λ, the amplitude of wave A₁ (not shown in FIG. 1), and alonger distance 2π/k₂ (along the x2 direction), associated with theseparation between adjacent “jogs” in the herringbone structure, whichwe refer to as the long wavelength. Other characteristic length are the‘jogs’ wavelength 2π/k₁ (along the x₁ direction, normal to the longwavelength direction x₂), the amplitude A₂ of the jogs, the jog angle θ.The bottom frames of FIG. 39 illustrate these features schematically.

Parts a-f of FIG. 40 show optical micrographs collected at differentstages during the formation of herringbone waves, for the case of ananomembrane with 100 nm thickness (lateral dimension of ca. 4×4 mm²)and thermal prestrain (defined by heating to 150° C.) of ˜3.8%. Theseimages indicate structure formation in two stages, the first of whichinvolves predominantly one-dimensional waves over large areas followedby bending of these wave structures to form, ultimately, compactherringbone layouts at full cooling (FIG. 40 d-f). FIG. 40 h shows thetime evolution of both characteristic wavelengths. The short wavelengthtends to decrease as the cooling leads to progressively largercompressive strain on the silicon due to the relatively larger thermalcontraction of the PDMS. In particular, this value decreases from 17-18μm in the initial stages to ˜14.7 μm when the herringbone structurebecomes prominent and finally to ˜12.7 μm in the fully cooled state.This wavelength is uniform (˜5% variation) over large areas. Bycontrast, the long wavelength associated with the herringbone layoutexhibits a broad range of values, as is evident from the image in FIG.40 g. Measurements at ˜100 spots across this sample yield a distributionof values, summarized in the histogram of FIG. 40 g. The herringbonestructure can be represented by an out-of-plane displacement w=A₁ cos[k₁x₁+k₁A₂ cos(k₂x₂)] (FIG. 49). Here the coefficients, amplitude ofwave A₁, long wavelength 2π/k₂, jogs wavelength 2π/k₁ and the amplitudeA₂ of the jogs are determined by analysis for a particular membranethickness, mechanical properties of the film, and substrate. The shortwavelength λ is (2π/k₁)sin(θ/2). The modeling uses the Si strain, asdetermined from measured contour lengths and periods of the wavystructures, as the applied prestrain, instead of the thermal prestain(FIG. 50). The actual strain that deforms the Si is typically somewhatsmaller than the estimated thermal prestain, due possibly to a loadingeffect of the Si on the PDMS. The Si strain, for example, is 2.4% at thethermal prestrain of 3.8%. For such a displacement w, the stress,strain, and displacement fields in the Si film can be obtained in termsof A₁, k₁, A₂, and k₂ from the Von Karman plate theory. The fields inthe PDMS substrate are obtained from 3D elasticity theory. Minimizingthe total energy, which consists of the membrane energy and bendingenergy in the Si film and the elastic energy in the PDMS substrate givesA₁, k₁, A₂, and k₂. The Young's modulus and Poisson's ratio of Si andPDMS are E_(Si)=130 GPa, v_(Si)=0.27, E_(PDMS)=1.8 MPa, andv_(PDMS)=0.5. Both the experiments and model give the jog angle θ to beabout 90°. The short wavelength given by the theory is 12.4 μm at 2.4%biaxial prestain, which agrees well with the experimental results above.The large variation in the long wavelength 2π/k₂ is also predicted bythe theoretical calculation, from 30 to 60 μm.

FIG. 41 presents atomic force microscope (AFM) and scanning electronmicroscope (SEM) images of structures similar to those illustrated inthe fully cooled state of FIG. 40. These images clearly show that theherringbone patterns are characterized by zigzag structures that definetwo characteristic directions, even though the compressive strain iscompletely isotropic. The herringbone structures represent a minimumelastic energy configuration that reduces the overall in-plane stress inthe system and relieves biaxial compression in both directions. Thisgeometry is, therefore, preferred over large areas, compared to the“checkerboard” and 1D wave layouts because the herringbone mode is theonly one of these three modes that relaxes the in-plane stress in alldirections without incurring significant stretch energy. Only in theimmediate vicinity of the jogs is significant stretch induced. The 1Dmode lowers the prestress only in one direction. The checkerboard modelowers the stress in all directions, but it produces significant stretchenergy accompanying the bending.

The two linecuts extracted from the AFM images indicate periodic,although only approximately sinusoidal, relief profiles along the jogsdirection (profile i) and perpendicular to waves (profile ii). The λ andA₁ of waves, determined from profile ii, are 12.8 and 0.66 μm,respectively. The λ given by theoretical analysis, 12.4 μm, is similarwith the experimental data; however, the A₁ from theoretical analysis is0.90 μm, somewhat higher value than the experimental results. The SEMimages show clearly the intimate bonding between the membrane and thePDMS, as evidenced by the behavior of the sample near the small holes inthe silicon in both the raised and recessed regions of the waves. Theseimages also indicate that the wave structures are completelyuncorrelated to the position of these holes, since the hole size of 2.5μm is much smaller than the characteristic wavelengths of thedeformation modes in our experiments. Studies of the dependence of thegeometry of the wavy structures on the thickness of the silicon canprovide additional insights into the physics and further validate themechanics models. FIG. 42 shows some results, including opticalmicrographs and wavelengths and amplitudes of wave structures formed inmembranes with different thicknesses for similar thermal strains. For100 nm thickness, the λ and A₁ of waves are 12.6 (±0.37) and 0.64(±0.07) μm, respectively, and for 320 nm thick, they are 45.1 (±1.06)and 1.95 (±0.18) μm. These values correspond reasonably well withtheoretical calculations, which yield the λ and A₁ are 12.4 and 0.90 μmfor the 100 nm case and 45.1 and 3.29 μm respectively, for the 320 nmcase.

These wavy membranes provide true stretchability for strains in variousin-plane directions, as opposed to the one-dimensional stretchabilityprovided by previously described ribbon geometries. To investigate thisaspect, we perform uniaxial tensile stretching tests along differentdirections using a calibrated mechanical stage and a 2D stretchablemembrane prepared with a thermally induced prestrain of 3.8%. FIG. 43provides some images. In case i, tensile stain (∈_(at)) applied alongthe direction of the long waves caused the herringbone structure to“unfold” (∈_(st)) 1.8%), gradually leading to a 1D wavy geometry at afully stretched state (∈_(st)) 3.8%). This stretching induces, by thePoisson effect, a compressive strain in the orthogonal direction with anamplitude roughly equal to half of the tensile strain. This compressivestrain can be accommodated by compression of the wavy structures in thisdirection. Upon release of the applied tensile strain, the originalherringbone waves recovered to exhibit structures quite similar to theoriginal. (FIG. 51 shows optical micrographs collected after 5, 10, and15 stretching cycles).

Tensile strains applied in a diagonal direction (case ii), showedsimilar structural changes although at full stretching the 1D wavestructures aligned along a direction defined by the applied strain,rather than the initial geometry. For the perpendicular case iii, atsmall strain ∈_(st) 1.8%) certain portions of the sample lose completelythe herringbone layout to yield new 1D waves along the stretchingdirection. With increasing strain, more regions undergo thistransformation until the entire area consists of these oriented 1Dwaves. These newly formed 1D waves are perpendicular to the orientationof the original waves; upon release, they simply bend to create adisordered herringbone-like geometry. For all cases shown in FIG. 43B,the wavelength increases with tensile strain and recovers to its initialvalue upon the release, even though compressive stresses are induced inthe orthogonal direction by the Poisson effect. This behavior arisesfrom an increase of λ induced by the unfolding of the herringbone wavesthat is larger than the decrease in this wavelength caused by thePoisson effect. (FIG. 52) For case i, the jogs wavelength, 2π/k₁ (FIG.52A) decreases to 2π/k′₁ (FIG. 52B), i.e., k′₁>k₁, under the appliedtensile strain, ∈_(st), due to the Poisson effect. However, thecorresponding jog angle θ′ is larger than the angle θ due to theunfolding of the herringbone structure. The short wavelength λ=(2π/k₁)sin(θ/2) becomes λ′=(2π/k′₁)sin(θ′/2), which may be larger than λ whenthe effect of angle change overcomes the Poisson effect. Our theoreticalmodel gives λ=12,4, 14.6, and 17.2 μm for ∈_(st)=0, 1.8, and 3.8%, whichconfirms that the short wavelength increases with the applied strain, asobserved in experiments. For case iii, both λ and 2π/k₁ increased withapplied stretching strain, since waves were relaxed along the directionof stretching strain, and the jogs angle (θ) was not changedsignificantly by the Poisson effect. The biaxial stretchability of thebuckled membranes was also investigated by thermally induced tensilestrains (FIG. 53). The herringbone waves generated by thermal strainslowly disappeared as the sample was heated; they recovered completelyupon cooling.

These observations apply only to the central regions of the membranes.As indicated in the bottom frames of FIG. 39, the edges of the membranesshow 1D wave structures with wavevectors oriented along the edges. AFMimages and linecut profiles of the edge region, the central region, andthe transition area between them are shown in FIG. 44. The 1D waves thatoriginate near the edge of the Si (top frame) gradually become bent(middle frame) until they transform into the herringbone geometries inthe central regions (bottom frame). The λ values in these regions are16.6, 13.7, and 12.7 μm, respectively (from top frame), with A₁ of 0.52,0.55, and 0.67 μm. Compared to the 1D waves at the edges, the 2Dherringbone waves have smaller X and A₁, suggesting that the inner areaof Si is affected more strongly by the compressive strain than theedges. The stress state near the edge is approximately uniaxialcompression within some distance range because of the traction-free edgeof the membrane. This uniaxial compression is parallel to this free edgeand therefore leads to 1D waves along the edge. The stress state,however, becomes equi-biaxial compressive in the central region whereherringbone structures result. For the transition area between the 1Dwavy edge and the herringbone waves, the unbalanced biaxial compressioncauses a “semi”-herringbone wave with the large jog angle. Our modelyields λ and A₁ of 16.9 and 0.83 μm, respectively, for the 1D waves and12.4 and 0.90 μm for the herringbone structure. These results agreereasonably well with the experimentally observed values.

To investigate further these edge effects, we fabricated rectangularmembranes with lengths of 1000 μm and with widths of 100, 200, 500, and1000 μm, all on the same PDMS substrate. FIG. 45 shows opticalmicrographs of these structures, for two different levels of thermalprestrain. At low thermal prestrain (ca. 2.3%, FIG. 45A), the 100 and200 μm wide membranes exhibit perfect 1D waves from one side to theother, with flat, undeformed regions at the ends. The 500 μm widemembrane shows similar 1D waves and flat regions, but the waves haveslightly bent geometries in the middle of the structures, with overallordering and uniformity in orientation that are substantially less thanthe 100 and 200 μm cases. For the 1000 μm square, 1D waves are presentin the central regions of the edges, with flat areas in the corners. Thecenter part of the membrane shows fully developed herringbonegeometries. For the corner flat region, there is an approximatelystress-free state due to the two free edges. No waves form near suchcorners. With increasing prestrain (4.8%, FIG. 45B), the flat regions inall cases decrease in size. 1D wavy behavior persists in the 100 and 200μm ribbons, but pronounced herringbone morphologies appear in thecentral region of the 500 μm case. At the higher prestrain, equi-biaxialcompressive strains are present in the inner region of 500 μm widemembrane. For the 1000 μm square membrane, the herringbone behaviorextends to regions close to the edges. The characteristic length scalesthat define the spatial extent of the flat regions, which we refer to asthe edge effect length, Ledge, can be evaluated as a function ofmembrane size and prestrain. FIG. 45C shows results that indicate alinear scaling of this length with prestrain, in a manner that isindependent of the size of the membrane, for the cases investigatedhere. As the prestrain becomes higher, the length of uniaxial strainregion becomes smaller. Therefore, shorter range 1D waves form andsimilar behavior can be observed in the stress-free regions near the twofree edges.

FIG. 46 shows optical micrographs of wavy structures that form in othermembrane geometries, including circles, ovals, hexagons, and triangles.The results are qualitatively consistent with observations in theribbons and squares of FIG. 45. In particular, the edge regions show 1Dwaves oriented parallel to the edges. Waves with the orthogonalorientation only appear at distances larger than the L_(edge) from theedge. For the circle, 1D waves appear near the edges, with an overallradial orientation due to the shape of the membrane. Herringbone wavesappear in the center. The ovals exhibit similar behavior, although withflat regions at the edges of the major axis, due to the small radius ofcurvature in these regions. For the hexagon and triangle shapes, thesharp corners (angles of 120° and 60°, respectively), lead to flatregions. Herringbone geometries appear in the center of the hexagons.The centers of the triangles show the merging of 1D waves, for the levelof prestrain shown here. For shapes with clear corners (e.g., hexagon,triangle, and tip of ellipse), there is no wave near the corner becausethe two intersecting free edges (not necessarily perpendicular) give astress-free state. For the triangle shape, there is not enough space togenerate the herringbone structure even in the central region.

The membranes themselves provide a path to biaxially stretchableelectronic devices. The edge effects outlined above can be exploited torealize a particular outcome that might be useful for certain classes ofsuch devices. In particular, in an imaging system, there might be valuein maintaining flat, undeformed regions at the locations of thephotodetectors to avoid nonideal behavior that occurs when these deviceshave wavy shapes. FIG. 47 presents some representative examples ofstretchable membranes that achieve this outcome. These structuresconsist of 100×100 μm square islands connected by 30 μm×150 μm ribbons(30 μm×210 μm for orthogonal ribbons) in the vertical and horizontaldirections (FIG. 47A, C), and in the vertical, horizontal and diagonaldirections (FIG. 47E, G). Changes in the amplitudes and wavelengths ofthe waves in the ribbons provide a means to accommodate applied strains,in a manner that largely avoids deformations in the regions of thesquare islands. We examined the behavior of these structures at severaldifferent applied strains. Parts a and e of FIG. 47 show representativecases in the low strain (ca. 2.3%) regime, applied by heating thesamples in an oven. Parts c and g of FIG. 47 show the same structures atrelatively high biaxial strains (ca. 15%), applied using a mechanicalstage. As is evident, in the low-strain regime the islands remain flat;at sufficiently high strains, wave structures begin to form in theseregions. Good adhesion between PDMS and Si was maintained at allstrains, as shown in the tilted angle SEM images (FIG. 47B, D, F, H).The insets of high-magnification SEM image in parts b and d of FIG. 47also confirm the strong bond of Si with PDMS.

In summary, nanomembranes of silicon can be integrated with prestrainedelastomeric substrates to create 2D “wavy” structures with a range ofgeometries. Many aspects of the mechanical behavior of these systems arein good agreement to theoretically predicted behaviors. These resultsare useful for applications of electronics in systems where fullstretchability is required during use or during installation.

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Example 4 Heterogeneously Integrated, Three Dimensional Electronics byUse of Printed Semiconductor Nanomaterials

We have developed a simple approach to combine broad classes ofdissimilar materials into heterogeneously integrated (HGI) electronicsystems with two or three dimensional (3D) layouts. The process beginswith the synthesis of different semiconductor nanomaterials (e.g. singlewalled carbon nanotubes and single crystal nanowires/ribbons of galliumnitride, silicon and gallium arsenide) on separate substrates. Repeatedapplication of an additive, transfer printing process using soft stampsand these substrates as donors, followed by device and interconnectformation, yields high performance 3D-HGI electronics that incorporateany combination of these (or other) semiconductor nanomaterials on rigidor flexible device substrates. This versatile methodology can produce awide range of unusual electronic systems that are difficult orimpossible to achieve using other techniques.

Many existing and emerging electronic devices benefit from themonolithic, heterogeneous integration (HGI) of dissimilar classes ofsemiconductors into single systems, in either two or three dimensional(2D or 3D) layouts. Examples include multifunctional radio frequencycommunication devices, infrared (IR) imaging cameras, addressable sensorarrays and hybrid CMOS/nanowire/nanodevice circuits (3-7). In somerepresentative systems, compound semiconductors or other materialsprovide high speed operation, efficient photodetection or sensingcapabilities while silicon CMOS provides digital readout and signalprocessing, in circuits that often involve stacked 3D configurations.Wafer bonding (8) and epitaxial growth (9,10) represent the two mostwidely used methods for achieving these types of 3D-HGI systems. Theformer process involves physical bonding, by use of adhesives orthermally initiated interface chemistries, of integrated circuits,photodiodes or sensors formed separately on different semiconductorwafers. This approach works well in many cases, but it has importantdrawbacks, including (i) limited ability to scale to large areas or tomore than a few layers in the third (i.e. stacking) dimension, (ii)incompatibility with unusual (e.g. nanostructured materials) or lowtemperature materials and substrates, (iii) challenging fabrication andalignment for the through-wafer electrical interconnects, (iv) demandingrequirements for flat, planar bonding surfaces and (v) bowing andcracking that can occur from mechanical strains generated bydifferential thermal expansion/contraction of disparate materials.Epitaxial growth provides a different approach that involves the directformation, by molecular beam epitaxy or other means, of thin layers ofsemiconductor materials on the surfaces of wafers of other materials.Although this method avoids some of the aforementioned problems, therequirements for epitaxy place severe restrictions on the quality andtype of materials that can be grown, even when buffer layers and otheradvanced techniques are used. By contrast, emerging classes ofsemiconductor nanomaterials, such as nanoscale wires, ribbons, membranesor particles of inorganic materials, or carbon based systems such assingle walled carbon nanotubes (SWNTs) or graphene sheets (11-14), canbe grown and then suspended in solvents or transferred onto substratesin a manner that bypasses the need for epitaxial growth or waferbonding. Recent work shows, for example, the integration, in 2D layouts,of crossed nanowire diodes formed by solution casting (15). The resultspresented here illustrate how dissimilar single crystal inorganicsemiconductors (e.g., nanowires/ribbons of GaN, Si and GaAs) can becombined with one another and also with other classes of nanomaterials(e.g. SWNTs) using a scalable and deterministic printing method to yieldcomplex, HGI electronic systems in 2D or 3D layouts. In particular,ultrathin multilayer stacks of high performancemetal-oxide-semiconductor field-effect transistors (MOSFETs),metal-semiconductor field-effect transistors (MESFETs), thin filmtransistors (TFTs), photodiodes and other components, integrated intodevice arrays, logic gates and actively addressable photodetectors onrigid inorganic and flexible plastic substrates demonstrate some of thecapabilities.

FIG. 57 illustrates representative steps for producing these 3D-HGIsystems. The process begins with synthesis of the semiconductornanomaterials, each on their own source substrate. The devices presentedhere integrate nanowires and nanoribbons of single crystal Si, GaN andGaAs, formed using wafer based source materials and lithographic etchingprocedures (16-21), and networks of SWNTs grown by chemical vapordeposition (13,21). Scanning electron micrographs at the top of FIG. 57show these semiconductor nanomaterials, after their removal from thesource substrates. For circuit fabrication, these elements remain in theconfigurations defined on the wafers during the fabrication or growthstage: aligned arrays in the case of the Si, GaN and GaAsnanowires/ribbons and sub-monolayer random networks for the SWNTs. Hightemperature doping and annealing procedures for ohmic contacts to theSi, GaN and GaAs can be performed on the source substrates. The nextstep involves transferring these processed elements, using anelastomeric stamp-based printing technique described previously, fromthe source substrates to a device substrate, such as a sheet ofpolyimide (PI) as illustrated in FIG. 57. In particular, laminating astamp of polydimethysiloxane (PDMS) against the source substrateestablishes soft, van der Waals adhesion contacts to the semiconductornanomaterial elements. Contacting the ‘inked’ stamp to a devicesubstrate (e.g. PI sheet) with a thin, spin-cast layer of a liquidprepolymer (e.g. polyamic acid) on its surface and then curing thepolymer leaves these semiconductor materials embedded on and welladhered to this layer (16-20) when the stamp is removed. Similarprocedures work well with a range of substrates (i.e. rigid or flexible;organic or inorganic) and semiconductor nanomaterials [A slightlymodified version of this process is used for the SWNTs (21).]. Thethickness of the interlayer (PI in this case) can be as small as 500 nmand is typically 1-1.5 μm, for the systems described here. After someadditional processing, including formation of gate dielectrics,electrodes and interconnects, the transfer printing and devicefabrication steps can be repeated, beginning with spin-coating a newprepolymer interlayer on top of the previously completed circuit level.Automated stages specially designed for transfer printing orconventional mask aligners enable overlay registration accuracy of ˜1 μmover several square centimeters. (22) (FIG. 61). Layer to layerinterconnects (23) are formed simply by evaporating metal lines over andinto openings in the interlayers defined by photopatterning and/or dryetching. This unusual approach to 3D-HGI electronics has severalimportant features. First, all of the processing on the device substrateoccurs at low temperatures, thereby avoiding differential thermalexpansion/shrinkage effects that can result in unwanted deformations inmultilayer stacked systems. This operation also enables the use of lowtemperature plastic substrates and interlayer materials, and it helps toensure that underlying circuit layers are not thermally degraded byprocessing of overlying devices. Second, the method is applicable tobroad classes of semiconductor nanomaterials, including emergingmaterials such as thin films of SWNT. Third, the soft stamps enablenon-destructive contacts with underlying device layers; these stamps,together with the ultrathin semiconductor materials, can also toleratesurfaces that have some topography. Fourth, the ultrathin devicegeometries (<1 μm) and interlayers (<1.5 μm) allow easy formation oflayer to layer electrical interconnects. These features, which overcomemany of the disadvantages of conventional approaches, are illustrated inthe several circuit demonstrations described in the following.

FIG. 58 presents a three layer, 3D stack arrayed Si MOSFETs fabricatedusing the general process flow illustrated in FIG. 57, using singlecrystal silicon nanoribbons, with doped contacts (formed on the sourcewafer), plasma enhanced chemical vapor deposited SiO2 dielectrics, andCr/Au metallization for source, drain and gate (24). Each device usesthree aligned nanoribbons, with widths, thicknesses and lengths of 87μm, 290 nm and 250 μm, respectively. FIG. 2A shows a top view opticalmicrograph of an edge of the system with a layout designed to revealseparately the parts of the substrate that support one, two and threelayers of MOSFETs. A ninety degree rotation of the device geometry forthe second layer, relative to the first and third, helps to clarify thelayout of the system. Schematic cross-sectional and angled views of thestacked structure appear in FIG. 58B. The sample can be viewed in 3Dusing confocal optical microscopy. FIG. 58C shows top and angled viewsof such images, colorized for ease of viewing. (The image qualitydegrades somewhat with depth, due to scattering and absorption from theupper layers). FIG. 58D presents electrical measurements ofrepresentative devices [top gate MOSFETs with channel lengths (L_(c)) of19 μm, channel overlap distances (Lo), defined by distance that the gateelectrode extends over the doped source/drain regions, of 5.5 μm, andchannel widths (W) of 200 μm] in each layer. Devices on each of thethree layers, which are formed on a PI substrate, show excellentproperties (linear mobilities of 470±30 cm²/Vs, on/off ratios >104 andthreshold voltages of −0.1±0.2V) and no systematic differences betweendevices in different layers. Additional layers can be added to thissystem, by repeating the same procedures. In addition to 3D circuitswith a single semiconductor, as illustrated in FIG. 59, varioussemiconductors can be used in multiple layers to form full 3D-HGIsystems. To illustrate this capability, we fabricated arrays of MESFETS(in particular, high electron mobility transistors, HEMTs), MOSFETs andTFTs using GaN and Si nanoribbons, and SWNT films, respectively, on PIsubstrates. FIGS. 59A and 59B show high magnification optical andconfocal images, respectively, of the resulting devices. The GaN HEMTson the first layer use ohmic contacts (Ti/Al/Mo/Au, annealed on thesource wafer) for source and drain, and a Schottky (Ni/Au) contacts forthe gates. The channel lengths and widths, and the gate widths are 20,170, and 5 μm respectively. Each device uses GaN ribbons (composed ofmultilayer stacks of AlGaN/GaN/AlN) with thicknesses, widths and lengthsof 1.2, 10 and 150 μm, respectively, interconnected electrically byprocessing on the device substrate. The SWNT TFTs on the second layeruse SiO₂/Epoxy for the gate dielectric and Cr/Au for source, drain andgate, with channel lengths and widths of 50 and 200 μm, respectively.The Si MOSFETs use the same design as those shown in FIG. 58. Variousother 3D-HGI devices can be constructed using different combinations ofSi, SWNT and GaN (FIGS. 61 and 62). FIG. 59C presents thecurrent-voltage characteristics of typical devices in the systems ofFIGS. 59A and 59B. In all cases, the properties are similar to thosefabricated on the source wafers: the GaN HEMTs have threshold voltages(V_(th)) of −2.4±0.2 V, on/off ratios >10₆, and transconductances of0.6±0.5 mS; the SWNT TFTs have V_(th)=−5.3±1.5 V, on/off ratios >105 andlinear mobilities of 5.9±2.0 cm²/Vs; the Si MOSFETs have V_(th)=0.2±0.3V, on/off ratios >10⁴ and linear mobilities of 500±30 cm²/Vs. Aninteresting aspect of these devices, which follows from the use of thinPI substrates (25 μm), devices (2.4 μm) and PI/PU interlayers (5 μm), istheir mechanical bendability, which is important for applications inflexible electronics. We evaluated the effective transconductance(g_(eff)) for the Si, SWNT, and GaN devices in the 3D-HGI system of FIG.59A as a function of bend radius. FIG. 59D, which shows these data, asnormalized to the transconductance in the unbent state (g_(0eff)),illustrates the stable performance for bend radii down to 3.7 mm.

Electrical interconnections formed between different levels in these3D-HGI devices can create interesting circuit capabilities. The thinpolymer interlayers enable these interconnects to be formed easily byevaporating metal lines over and into lithographically defined openings.FIG. 60 presents some examples. The first, shown in FIG. 60A, is a 3DNMOS inverter (logic gate) in which the drive (L=4 μm, W=200 μm) andload (L=4 μm, W=30 μm) Si MOSFETs are on different levels. With a supplyvoltage of 5V, this double-layer inverter exhibits well-defined transfercharacteristics with gains of ˜2, comparable to the performance ofconventional planar inverters that use the similar transistors (25).FIG. 60B shows an inverter with a complementary design (CMOS) by use ofintegrated n-channel Si MOSFETs and p-channel SWNT TFTs, designed inorder to equalize the current-driving capability in both pull-up andpull-down directions (FIG. 65). Transfer curves collected with a 5 Vbias to the VDD terminal and gate voltage (input) swept from 0 V to 5 Vappear in FIG. 60A. The curve shapes and gains (as high as ˜7) arequalitatively consistent with numerical circuit simulations (FIG. 65).As a third example, we built GaAs metal-semiconductor-metal (MSM)infrared (IR) detectors (26) integrated with Si MOSFETs on flexible PIsubstrates, to demonstrate a capability for fabricating unit cells thatcould be used in active IR imagers. In this case, printed nanoribbons ofGaAs (thicknesses, widths and lengths of 270 nm, 100 μm and 400 μm,respectively) transferred onto a substrate with a printed array of Sinanoribbon MOSFETs form the basis of the MSMs. Electrodes (Ti/Au=5/70nm) deposited on the ends of these GaAs nanoribbons form back-to-backSchottky diodes with separations of 10 μm. The resulting detector cellsexhibit current enhancement as the intensity of IR illuminationincreases (FIG. 60C), consistent with circuit simulation (FIG. 66). Aresponsivity of about 0.30 A/W at the 850 nm wavelength is observed from1 to 5 V, without taking into account the light reflected from thesurface of the semiconductor. The system also exhibits bendability withradii of curvature below 1 cm, which could be useful for advancedsystems such as curved focal plane arrays for wide angle IR night visionimagers.

Printed semiconductor nanomaterials provide new approaches to 3D-HGIsystems and could have important applications in various fields ofapplication, not only those suggested by the systems reported here, butalso others including microfluidic devices with integrated readout andsensing electronics, chem/bio sensor systems that incorporate unusualsensing materials with conventional silicon based electronics andphotonic/optoelectronic systems that combine light emitters of compoundsemiconductor with silicon drive electronics or microelectromechanicalstructures. Further, the compatibility of this approach with thin,lightweight plastic substrates may create additional opportunities fordevices that have unusual form factors or mechanical flexibility as keyfeatures.

Materials and Methods:

Device fabrication: Silicon devices: The fabrication begins withdefinition of contact doped thin ribbons of single crystal silicon, byprocessing silicon on insulator wafer (SOI; Soitec unibond with a 290 nmtop Si layer with doping level of 6.0˜9.4×10¹⁴/cm³). The first stepinvolved phosphorous doping, using a solid source and spin-on-dopant(Filmtronic, P509), and a photolithographically defined layer of plasmaenhanced chemical vapor (PECVD) deposited SiO₂ (Plasmatherm, 300 nm, 900mTorr, 350 sccm, 2% SiH₄/He, 795 sccm NO₂, 250° C.) as a mask to controlwhere dopant diffuses into the silicon. After doping, SF₆ plasma etchingthrough a patterned layer of photoresist defined the ribbons. Undercutetching of the buried oxide with concentrated HF solution (FisherChemicals) released the ribbons from the wafer. This procedure completedthe fabrication of contact doped ribbons of single crystal silicon. Inthe next step, contacting a flat elastomeric stamp ofpolydimethylsiloxane (PDMS, A:B=1:10, Sylgard 184, Dow Corning) with thephotoresistcoated ribbons and then peeling back the stamp removed theribbons from the wafer and left them adhered, by van der Waals forcesbetween the hydrophobic PDMS and the photoresist, to the surface of thestamp. The stamp thus ‘inked’ with s-Si ribbons from wafer was laminatedagainst a polyimide (PI) sheet of 25 μm (Dupont, Kapton100E) spincoatedwith a thin layer (˜1.5 μm) of liquid PI precursor, polyamic acid(Sigma_Aldrich Inc.). Curing the precursor, peeling off the PDMS stamp,and stripping the photoresist left the ribbons embedded on and welladhered to the surface of the PI substrate. The gate dielectric layerconsisted of a layer of SiO₂ (thickness ˜100 nm) deposited by PECVD atrelatively low temperature, 250° C. Photolithography and CF₄ plasmaetching defined openings to the doped source/drain regions of thesilicon. Source, drain and gate electrodes of Cr/Au (5/100 nm, frombottom to top by electron beam evaporation, Temescal FC-1800) weredefined in a single step by photolithography and wet etching.

GaN Devices:

GaN microstructures were fabricated on a bulk wafer of GaN withheteorostructure [AlGaN(18 nm)/GaN(0.6 μm)/AlN(0.6 μm)/Si]. An ohmiccontact area defined by AZ 5214 photoresist and then cleaned with SiCl₄plasma in a RIE system. A Ti/Al/Mo/Au (15/60/35/50 nm) metal layer wasthen deposited by e-beam evaporation (Ti/Al/Mo) and thermal evaporation(Au). Washing away the resist completed left metal contacts on the GaN.Thermal annealed at 850° C. for 30 sec in N₂ ambient formed the ohmics.SiO2 (Plasmatherm, 300 nm, 900 mTorr, 350 sccm, 2% SiH4/He, 795 sccmNO₂, 250° C.) and Cr metal (e-beam evaporator, 150 nm) layers weredeposited as the mask materials for subsequent inductively coupledplasma (ICP) etching. Photolithography, wet etching, and RIE processing(50 mTorr, 40 sccm CF4, 100 W, 14 min) defined the ribbon geometries ofthe GaN. After removing the photoresist with acetone, ICP dry etching(3.2 mTorr, 15 sccm Cl2, 5 sccm Ar, −100V Bias, 14 min) was used toremove the exposed GaN and to etch slightly into the Si (˜1.5 μm) tofacilitate the subsequent anisotropic etching. The Si was then etchedaway from underneath the GaN using a tetramethyl ammonium hydroxide(Aldrich, 150° C. for 4 min 30 sec). The sample was dipped in BOE (6:1,NH₄F:HF) for 30 sec to remove the PECVD SiO₂ and a new 50 nm e-beamevaporated SiO2 layer was deposited on top of the GaN ribbons. A PDMSslab ‘inked’ with the GaN ribbons from mother wafer was then laminatedagainst a PI sheet coated with 2 μm polyurethane (PU, Norland opticaladhesive, No. 73). The sample was exposed to UV light (173 μWcm⁻²) for15 min to cure the PU. Peeling back the PDMS and removing the e-beamSiO2 by immersion in BOE for 20 sec resulted in the transfer of the GaNelements to the plastic substrate. A negative photoresist (AZ nLOF2020)was used to pattern Schottky contacts of Ni/Au (80/180 nm). Thephotoresist was removed with an AZ stripper (KWIK for 30 min).

SWNT Devices:

Chemical vapor deposition (CVD) was used to grow random networks ofindividual single walled carbon nanotubes on SiO2/Si wafers. Ferritin(Sigma Aldrich) deposited on the substrate with a methanol was used as acatalyst. The feeding gas was methane (1900 sccm CH₄ with a 300 sccmH₂). The quartz tube in the furnace was flushed with a high flow of Argas for cleaning before growth. During the growth, the temperature washeld at 900° C. for 20 minutes. The transfer involved either proceduressimilar to the printing like processes described previously, or aslightly different method in which a thick Au layer and a PI precursorwere coated on the SiO₂/Si substrate with the tubes. After curing thePI, the Au/PI was peeled back. Laminating this layer against aprepatterned device substrate coated with a thin epoxy layer (SU8, 150nm) and then removing the PI and Au layer by oxygen reactive ion etchingand wet etching, respectively, completed the transfer. In the case ofbottom gate devices, the substrate supported prepatterned gateelectrodes and dielectrics. In particular, gate electrodes of Cr/Au/Cr(2/10/10 nm) were patterned by photolithography and then, 300 nm SiO₂was deposited on the substrate using PECVD. The source and drainelectrodes of Cr/Au (2/20 nm) were defined directly on top of the tubes.

3D Circuit:

3D Si NMOS inverter: Multilayer devices were constructed by repetitivelyapplying the same fabrication procedures. In particular, to the PIprecursor was spin-cast on the top of an existing layer of devices, andsilicon ribbons were transfer-printed on top. The same processes werethen used to fabricate devices. For vertical metal interconnects, anelectrode area was defined by photo-patterning openings in a layer ofAZ4620 photoresist, and then etching away the SiO₂ and PI in thisexposed area using CF₄ and O₂ plasma in a RIE system. Depositing 300 nmAl into this area established contacts at the bottom, and provided anelectrically continuous connection over the step edge formed by theetched SiO₂ and PI.

SWNT and Si CMOS Inverter:

The SWNT devices consisted of source/drain contacts of Au (20 nm)defined by photolithography on the tube networks. The SiO₂ (100 nm)/Siwafer substrate provided the gate dielectric and gate. Epoxy (SUB, 500nm) was then spin-coated onto this substrate after the SWNT transistorswere selectively coated with photoresist (AZ5214). After UV exposure forcuring of epoxy, a PDMS slab ‘inked’ with undoped Si ribbons waslaminated against the substrate and subsequently removed by slow manualpeeling to complete the transfer-printing process. Cr/Au (5/100 nm) wereused as Schottky contacts for source and drain electrodes in the silicondevices. Al (100 nm) was used to connect the SWNT and Si transistor.

GaAs MSM IR Detector Integrated with Si TFT:

GaAs wafers (IQE Inc., Bethlehem, Pa.) were used to generateback-to-back schottky diodes. The ribbons were generated from ahigh-quality bulk wafer of GaAs with multiple epitaxial layers [Si-dopedn-type GaAs(120 nm)/semi-insulating(SI)-GaAs(150 nm)/AlAs(200nm)/SI—GaAs]. The carrier concentration of n-type GaAs is 4×10¹⁷ cm⁻³.GaAs wafers with photoresist mask patterns were anisotropically etchedin the etchant (4 mL H3PO4 (85 wt %), 52 mL H2O2 (30 wt %), and 48 mLdeionized water). The AlAs layers were etched away with a diluted HFsolution in ethanol (1:2 in volume). Layers of 2 nm Ti and 28 nm SiO2were the deposited by e-beam evaporator. A PDMS stamp inked with theGaAs ribbons was then contacted to a layer of Si transistors coated withPI (thickness 1.5 μm). Peeling back the PDMS and removing Ti and SiO₂ byBOE etchant completed the transfer of GaAs to the device substrate.Metals (Ti/Au=5/70 nm) for the Schottky contacts were deposited bye-beam evaporation. Electrical interconnects between the GaAsback-to-back Schottky diodes and the Si MOSFET were defined by firstpatterning a layer of AZ4620 photoresist, then etching through theopenings using CF₄ and O₂ plasma in a RIE system and then depositing a300 nm of Al.

Device Characterization:

A semiconductor parameter analyzer (Agilent, 4155C) and a conventionalprobing station were used for the electrical characterization of thediodes and transistors. The IR response was measured under IR LED sourcewith wavelength of 850 nM.

Circuit Simulation:

To compare the measured transfer curve of the CMOS inverter with asimulation, level 2 PSPICE models for the n-channel Si MOSFET and thep-channel SWNT TFT were generated empirically. These PSPICE models werecreated based on the default PSPICE MOSFET model (MbreakN and MbreakP)with extracted parameters to fit the measured IV curves of both Si NMOSand SWNT PMOS shown in FIG. 65B. The PSPICE model for GaAs MSMphoto-detector was created empirically using back-to-back schottkydiodes connected in series with Si MOSFET.

REFERENCES FOR EXAMPLE 4

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The pop up architecture is one that enables a range of devicearchitectures and structures integrating structures that embed usefulbut difficult to achieve features. It is an architecture enablingimportant competencies devices that express electronic, optical,mechanical, and thermal forms of functionality. In many cases, thesystem designs exploit a hierarchy of such effects to enable explicitdevice level performance outcomes, although for simplicity we discussspecific embodiments below in terms of a dominant mode of functioning.

Electronic Systems.

The most direct form of utility in this sphere is the provisions thedescribed architectures make for the design of complex mechanicallycompliant electronic devices that directly embed high performanceelectronic circuits-displays, sensing elements, RF-ID tags comprisingsome challenging forms of application that benefit from the integrationof high performance electronic circuits within a flexible system levelarchitecture. The designs disclosed herein significantly extend the fullrange of mechanical compliances that can be realized. It does so byenabling the provision, at the system design level, of specificarchitectural details that can extend range of mechanical deformationsthat can be tolerated—well beyond the general limit of 1% strain that istypical for a device based on a planar integration of components. Theexamples show a specific architecture for the simplest system elements,the interconnects, that can be used to withstand formal system highlevel strains (>30% in the form factor appropriate for the constructionof bus lines and interconnects in a display) as well as providing forother more demanding forms of mechanical compliance (stretchability).These benefits can be extended as well to more complex device levelcomponents as illustrated by the form factor of the exemplary devicesshown in FIG. 31, a GaAs MSM IR photodetector as described. Essentiallyevery functional component of a complex electronic system can beintegrated in a design-specific, mechanically compliant form using themethods taught herein.

Optical Components and Systems.

Optical components, e.g., a waveguide can respond with extremesensitivity to flexure. The methods and systems provide newarchitectures for such devices that can both tolerate and, moreimportantly, exploit mechanical flexure to benefit functionalperformance. Examples of technologies that can directly exploit themethods disclosed herein include advanced forms of photonic componentsincluding, but not limited to, waveguide optical couplers and relatedforms of optical switches and limiters. Mechanical flexure at the systemlevel of the integrated structure (via compression or extension)provides a direct means to effect these functionalities. The loss in achannel as well directly relates to the flexure of the waveguide-highbending radii promoting leakage in a controllable way from core tosheath modes. Such effects can be directly exploited in a variety ofdevices. For example, FIG. 67 schematically illustrates a waveguidearray produced via the controlled buckling of an optical microstructurepartially adhered to a deformable substrate. FIG. 67A shows the opticaldevice is produced by attaching a component 330 (e.g., waveguide such asan optical fiber or other elongated microstructure) to a substrate 30 bycontact printing, for example. The attachment includes strongly boundcontacting regions 310 and weakly bound regions corresponding to raisedregions 320. Upon deformation the second electrode buckles and theweakly-bound region of the waveguide separates physically from thesubstrate, thereby producing the raised region. The device may operatesimply as a waveguide capable of significant (5 to 50%) stretchability(see FIG. 67B). Alternatively, the indices of refraction of thewaveguide and substrate as well as the buckling geometry may be chosensuch that the device operates as an optical switch, allowing light topass in the elongated state (FIG. 67B) but not in the shortened state(FIG. 67A), due to the high curvature in the buckled waveguides.

Mechanically Functional Systems.

The intersection between mechanics and electronics is fundamental forseveral critical classes of technologies—inertial and other forms offorce sensors comprise specific examples that are both of currentinterest and finding broad use. The methods and systems disclosed hereinprovide a route to generating new forms of such devices. FIG. 68 is arepresentative example of a mechanical system, specifically an entwinedmultilayer architecture for capacitively coupled sensing. This exemplaryarchitecture directly enables important forms of force relatedsensing—inertial and pressure measurements most notably. In each casethe methods and systems disclosed herein provide a relatively directmeans to control many systems level aspects of the performance of thesedevices—dynamic range and region of optimum sensitivity mostnotably—while enabling their integration into compact, novel form-factorsystems (e.g. by allowing the integration of the electronic systems innew ways). These structures compliment established MEMS based approachesto devices of this type. Referring to FIG. 68, a mechanical device 400(e.g., accelerometer/pressure sensor) is produced via the controlledbuckling of a conductive microstructure partially adhered to adeformable substrate 30. This device architecture operates by monitoringchanges in the capacitance between the bottom electrode 450 and theother electrode 440 that occur when the raised region 320 of theelectrode 440 is displaced relative to the substrate via acceleration orpressure in the z-direction. The device 400 is produced by preparing anelectrode (bottom electrode 450) on the substrate 30, then by attachinganother electrode 440 by contact printing. The attachment includesstrongly bound contacting regions 310 and weakly bound regions (e.g., inthe region below 320). Upon deformation, the second electrode 440buckles and the weakly-bound region separates physically from thesubstrate, thereby producing the raised region 320.

Thermally Functional Devices.

The pop up structures afforded by the present invention engender newcapacities to provide for the thermal isolation of complex electroniccomponents. An explicit device class provides a general design for thepixel elements of a long wavelength imaging system that requires theintegration of high performance electronic components that providecontrol, read out, data handling and other capabilities for the systemwhile providing direct integration and precise thermal isolation ofthermally responsive (and for this example) two terminal devices. Thisdemanding architecture is readily accessed using the methods taught bythe current invention. In the present case it is possible to placefunctional electronic components—such as the AD converter needed to reada pixel—in close proximity to the IR responsive elements (appropriateexamples include but are not limited to Si and thin film multilayers ofphotoresistive metal oxides supported on Si₃N₄ membrane), a feature thatmakes it possible to both simplify design and enhance performance. Mostnotably, the systems and devices presented herein provides a capabilityof integrating of such device elements in a non-planar focal array. FIG.69 shows a thermal device 500 (microbolometer) produced via thecontrolled buckling of a thermoresistive microstructure partiallyadhered to a deformable substrate. The device 500 is produced byattaching to the substrate 30 an electrode 550 that contains athermoresistive material 560 by contact printing. The attachmentincludes strongly bound contacting regions 310 and weakly bound regionscorresponding to raised regions 320. Upon deformation, the electrode 550buckles and the weakly-bound region separates physically from thesubstrate, thereby producing the raised region 320 that is to a largeextent thermally isolated from the substrate, thereby providing accurateand localized temperature sensing.

U.S. patent application Ser. Nos. 11/115,954, 11/145,574, 11/145,542,60/863,248, 11/465,317, 11/423,287, 11/423,192, and 11/421,654 arehereby incorporated by reference to the extent not inconsistent with thepresent description.

All references throughout this application, for example patent documentsincluding issued or granted patents or equivalents; patent applicationpublications; and non-patent literature documents or other sourcematerial; are hereby incorporated by reference herein in theirentireties, as though individually incorporated by reference, to theextent each reference is at least partially not inconsistent with thedisclosure in this application (for example, a reference that ispartially inconsistent is incorporated by reference except for thepartially inconsistent portion of the reference).

The terms and expressions which have been employed herein are used asterms of description and not of limitation, and there is no intention inthe use of such terms and expressions of excluding any equivalents ofthe features shown and described or portions thereof, but it isrecognized that various modifications are possible within the scope ofthe invention claimed. Thus, it should be understood that although thepresent invention has been specifically disclosed by preferredembodiments, exemplary embodiments and optional features, modificationand variation of the concepts herein disclosed may be resorted to bythose skilled in the art, and that such modifications and variations areconsidered to be within the scope of this invention as defined by theappended claims. The specific embodiments provided herein are examplesof useful embodiments of the present invention and it will be apparentto one skilled in the art that the present invention may be carried outusing a large number of variations of the devices, device components,methods steps set forth in the present description. As will be obviousto one of skill in the art, methods and devices useful for the presentmethods can include a large number of optional composition andprocessing elements and steps.

Every formulation or combination of components described or exemplifiedherein can be used to practice the invention, unless otherwise stated.

Whenever a range is given in the specification, for example, atemperature range, a time range, or a composition or concentrationrange, all intermediate ranges and subranges, as well as all individualvalues included in the ranges given are intended to be included in thedisclosure. It will be understood that any subranges or individualvalues in a range or subrange that are included in the descriptionherein can be excluded from the claims herein.

All patents and publications mentioned in the specification areindicative of the levels of skill of those skilled in the art to whichthe invention pertains. References cited herein are incorporated byreference herein in their entirety to indicate the state of the art asof their publication or filing date and it is intended that thisinformation can be employed herein, if needed, to exclude specificembodiments that are in the prior art. For example, when composition ofmatter are claimed, it should be understood that compounds known andavailable in the art prior to Applicant's invention, including compoundsfor which an enabling disclosure is provided in the references citedherein, are not intended to be included in the composition of matterclaims herein.

As used herein, “comprising” is synonymous with “including,”“containing,” or “characterized by,” and is inclusive or open-ended anddoes not exclude additional, unrecited elements or method steps. As usedherein, “consisting of” excludes any element, step, or ingredient notspecified in the claim element. As used herein, “consisting essentiallyof” does not exclude materials or steps that do not materially affectthe basic and novel characteristics of the claim. In each instanceherein any of the terms “comprising”, “consisting essentially of” and“consisting of” may be replaced with either of the other two terms. Theinvention illustratively described herein suitably may be practiced inthe absence of any element or elements, limitation or limitations whichis not specifically disclosed herein.

One of ordinary skill in the art will appreciate that startingmaterials, biological materials, reagents, synthetic methods,purification methods, analytical methods, assay methods, and biologicalmethods other than those specifically exemplified can be employed in thepractice of the invention without resort to undue experimentation. Allart-known functional equivalents, of any such materials and methods areintended to be included in this invention. The terms and expressionswhich have been employed are used as terms of description and not oflimitation, and there is no intention that in the use of such terms andexpressions of excluding any equivalents of the features shown anddescribed or portions thereof, but it is recognized that variousmodifications are possible within the scope of the invention claimed.Thus, it should be understood that although the present invention hasbeen specifically disclosed by preferred embodiments and optionalfeatures, modification and variation of the concepts herein disclosedmay be resorted to by those skilled in the art, and that suchmodifications and variations are considered to be within the scope ofthis invention as defined by the appended claims.

TABLE 1 Parameters extracted (from experiments and calculations) fromthe buckles as shown in FIG. 31A. The calculations assume that thewidths (i.e., 10 μm for the samples shown in the figure) of theactivated regions are the same before and after stretching. measuredcalculated measured calculated calculated width width amplitudeamplitude peak strain pre-strain (μm) (μm) Am (μm) Acal (μm) εpeak (%)11.3% 136.6 170.7 37.5 37.6 0.38 25.5% 139.6 151.4 51.5 50.3 0.65 33.7%140.1 142.1 56.4 54.3 0.80 56.0% 124.3 121.8 63.6 60.4 1.2

TABLE 2 Parameters extracted (from experiments and calculations) fromthe buckles as shown in FIG. 31D measured calculated measured calculatedcalculated Win wavelength wavelength amplitude amplitude peak strain(μm) λm (μm) λcal (μm) Am (μm) Acal (μm) εpeak (%) 100 N/A 69 N/A 33.22.5 200 123 131 66.3 64.1 1.2 300 199 194 100.6 94.9 0.80 400 253 256129.3 128.8 0.61

1. (canceled)
 2. A two-dimensional device array comprising: a flexiblesubstrate having a supporting surface; at least one device componentsupported on the supporting surface; and at least two stretchableinterconnects, each of the at least two stretchable interconnects havinga first end, a second end, and a central portion that is between thefirst end and the second end, wherein the at least one device componentand the at least two stretchable interconnects are oriented in at leasttwo different directions to form the two-dimensional array, wherein thefirst end of each of the at least two stretchable interconnects is inelectrical communication with the at least one device component, whereinthe central portion of each of the at least two stretchableinterconnects comprises at least two bent configuration regions, andwherein each bent configuration region is not in physical contact withthe supporting surface of the flexible substrate.
 3. The two-dimensionaldevice array of claim 2, wherein each bent configuration region iscurved.
 4. The two-dimensional device array of claim 2, wherein thecentral region of each of the at least two stretchable interconnectscomprises at least one contact region that is in physical contact withthe supporting surface of the substrate, and wherein the at least onecontact region is located between the at least two bent configurationregions.
 5. The two-dimensional device array of claim 4, wherein the atleast one contact region is bonded to the supporting surface of thesubstrate.
 6. The two-dimensional device array of claim 2, wherein theat least one device component comprises one or more materials selectedfrom the group consisting of: a metal, a semiconductor, an insulator, apiezoelectric material, a ferroelectric material, a magnetostrictivematerial, an electrostrictive material, a superconductor, aferromagnetic material, and a thermoelectric material.
 7. Thetwo-dimensional device array of claim 2, wherein the at least one devicecomponent is an electronic device, an optical device, an opto-electronicdevice, a mechanical device, a microelectromechanical device, ananoelectromechanical device, a microfluidic device and a thermaldevice.
 8. The two-dimensional device array of claim 7, wherein the atleast two stretchable interconnects are tunable device components eachhaving at least one electronic property, optical property or mechanicalproperty that changes selectively with a level of strain of the centralportion provided by the at least two bent configuration regions.
 9. Thetwo-dimensional device array of claim 2, wherein the at least one of theat least two stretchable interconnects is a plurality of stretchableinterconnects, and wherein the plurality of stretchable interconnectshas a bridge configuration that comprises a central region that is inphysical contact with the supporting surface and three or more of theplurality of stretchable interconnects extending from the centralregion.
 10. The two-dimensional device array of claim 2, wherein each ofthe at least two stretchable interconnects further comprises one or morecontact pads in electrical contact with the first end, the second end orboth the first end and the second end.
 11. The two-dimensional devicearray of claim 10, wherein the at least one device component is inelectrical contact with the one or more contact pads.
 12. Thetwo-dimensional device array of claim 2, wherein each of the at leasttwo stretchable interconnects has a coiled conformation, a wrinkledconformation, a buckled conformation and/or a wavy configuration. 13.The two-dimensional device array of claim 2, wherein each of the atleast two bent configuration regions comprises a folded region, a convexregion, a concave region, or any combination thereof.
 14. Thetwo-dimensional device array of claim 2, wherein the flexible substratecomprises an elastomeric material.
 15. The two-dimensional device arrayof claim 2, wherein the at least one device component is a plurality ofdevice components, and wherein the at least two stretchableinterconnects is a plurality of stretchable interconnects.
 16. Thetwo-dimensional device array of claim 15, wherein the device array has agrid configuration, floral configuration, bridge configuration, or anycombination thereof.
 17. The two-dimensional device array of claim 15,wherein one or more of the plurality of device components is connectedto adjacent device components by the plurality of stretchableinterconnects.
 18. The two-dimensional device array of claim 17 whereinat least one of the plurality of stretchable interconnects is orientedin a direction that is different from another of the plurality ofstretchable interconnects.
 19. The two-dimensional device array of claim15, wherein at least a portion of the device array comprises two or moreof the plurality of stretchable interconnects aligned in a directionparallel to each other or two or more of the plurality of stretchableinterconnects oriented in two or more different directions.
 20. Thetwo-dimensional device array of claim 15, wherein the device arraycomprises two or more device layers, and wherein each device layercomprises a plurality of the device components and a plurality of thestretchable interconnects.
 21. The two-dimensional device array of claim15, wherein at least a portion of the supporting surface of the flexiblesubstrate is curved, concave, convex or hemispherical.
 22. Thetwo-dimensional device array of claim 15, wherein the device arraycomprises one or more of a photodetector, a photodiode array, a display,a light-emitting device, a photovoltaic device, a sensor array, a sheetscanner, a LED display, a semiconductor laser array, an optical imagingsystem, a large-area electronic device, a transistor array, a logic gatearray, a microprocessor, an integrated circuit, or any combination ofthereof.